TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 83

IC MCU 8BIT FLASH 60KB 80-LQFP

TMP86FS28DFG(JZ)

Manufacturer Part Number
TMP86FS28DFG(JZ)
Description
IC MCU 8BIT FLASH 60KB 80-LQFP
Manufacturer
Toshiba
Series
TLCS-870/Cr
Datasheet

Specifications of TMP86FS28DFG(JZ)

Core Processor
870/C
Core Size
8-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LCD, PWM, WDT
Number Of I /o
62
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Processor Series
TLCS-870
Core
870/C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SIO, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
62
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
TMP86FS28DFGJZ

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMP86FS28DFG(JZ)
Manufacturer:
Toshiba
Quantity:
10 000
6. Watchdog Timer (WDT)
6.1 Watchdog Timer Configuration
rious noises or the deadlock conditions, and return the CPU to a system recovery routine.
rupt request”. Upon the reset release, this signal is initialized to “reset request”.
rupt.
Internal reset
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu-
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “inter-
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter-
Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to
fc/2
fc/2
fc/2
fc/2
23
21
19
17
or fs/2
or fs/2
or fs/2
effect of disturbing noise.
or fs/2
15
13
11
9
WDTT
2
0034
WDTEN
Watchdog timer control registers
H
WDTCR1
Figure 6-1 Watchdog Timer Configuration
Clock
Clear
S R
Q
Binary counters
Writing
disable code
1
Controller
0035
2
H
WDTCR2
Overflow
Page 71
Writing
clear code
WDT output
WDTOUT
Reset release
Interrupt request
R
S
Q
TMP86FS28DFG
Reset
request
INTWDT
interrupt
request

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