TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 79

• Manufacturer Part Number: TMP86FS28DFG(JZ)
• Description: IC MCU 8BIT FLASH 60KB 80-LQFP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FS28DFG(JZ)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FS28DFGJZ

5.8 Port P7 (P70 to P77)
register (P7LCR) to “0”.
P7OUTCR to “0”.
for each bit in P7OUTCR.
state can be read from the P7PRD register.
Port P7 is an 8-bit input/output port that can also be used for LCD segment output.
A reset initializes the output latch (P7DR) to “1”, the Pch control (P7OUTCR) to “0”, and the LCD output control
To use a pin in Port P7 as an input port, set P7DR to “1” and then set the corresponding bit in P7LCR and
To use a pin in Port P7 as an LCD segment output, set the corresponding bit in P7LCR to “1”.
The output circuit of Port P7 can be set either as sink open-drain output (“0”) or CMOS output (“1”) individually
Port P7 has a separate data input register. The output latch state can be read from the P7DR register, and the pin
Note: An asterisk (*) indicates that either “1” or “0” can be set.
Output latch read (P7DR)
Data input (P7PRD)
Data output (P7DR)
Table 5-10 Register Programming for Port P7 (P70 to P77)
Port input
Port “0” output
Port “1” output
LCD segment output
P7OUTCRi input
LCD data output
P7LCRi input
P7OUTCRi
P7LCRi
OUTEN
STOP
Function
Output latch
D
D
D
Figure 5-9 Port P7
Q
Q
Q
Page 67
P7DR
“1”
“0”
“1”
*
Programmed Value
appropriate.
P7OUTCR
Set as
“0”
*
P7LCR
“0”
“0”
“0”
“1”
P7i
Note) i = 7~0
TMP86FS28DFG