TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 70

• Manufacturer Part Number: TMP86FS28DFG(JZ)
• Description: IC MCU 8BIT FLASH 60KB 80-LQFP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FS28DFG(JZ)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FS28DFGJZ

5.3 Port P2 (P20 to P22)
5.3 Port P2 (P20 to P22)
Read only
(0FF2H)
(0002H)
P2PRD
input, or low-frequency resonator connection.
kHz). In the single clock mode, pins P21 and P22 can be used as normal input/output port pins.
(When P20 is used as an output port, the interrupt latch is set on the falling edge of the output pulse.)
state can be read from the P2PRD register.
P2DR
R/W
Port P2 is a 3-bit input/output port that can also be used for external interrupt input, STOP mode release signal
To use Port P2 as an input port or function pins, set the output latch (P2DR) to “1”. A reset initializes P2DR to “1”.
In the dual clock mode, pins P21 (XTIN) and P22 (XOUT) are connected with a low-frequency resonator (32.768
It is recommended that pin P20 be used as an external interrupt input, STOP release signal input, or input port.
Port P2 has a separate data input register. The output latch state can be read from the P2DR register, and the pin
When a read instruction is executed on P2DR or P2PRD, bits 7 to 3 are read as undefined.
Note: Since pin P20 is also used as a
Output latch read (P21)
Output latch read (P22)
Data input (P20PRD)
Data input (P21PRD)
Data input (P22PRD)
OUTEN state.
Data output (P20)
Data output (P21)
Data output (P22)
Data input (P20)
7
7
Control input
OUTEN
STOP
XTEN
6
6
fs
5
5
Output latch
Output latch
Output latch
D
D
D
STOP
4
4
Q
Q
Q
Figure 5-4 Port P2
pin, the output of P20 becomes high-impedance in STOP mode regardless of the
3
3
Page 58
XTOUT
P22
P22
2
2
XTIN
P21
P21
1
1
Osc. enable
STOP
P20
INT5
P20
0
0
(Initial value: **** *111)
P20 (INT5, STOP)
P21 (XTIN)
P22 (XTOUT)
TMP86FS28DFG