TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 65
TMP86FS28DFG(JZ)
Manufacturer Part Number
TMP86FS28DFG(JZ)
Description
IC MCU 8BIT FLASH 60KB 80-LQFP
Manufacturer
Toshiba
Series
TLCS-870/Cr
Datasheet
1.TMP86FS28DFGJZ.pdf
(272 pages)
Specifications of TMP86FS28DFG(JZ)
Core Processor
870/C
Core Size
8-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LCD, PWM, WDT
Number Of I /o
62
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Processor Series
TLCS-870
Core
870/C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SIO, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
62
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
TMP86FS28DFGJZ
Available stocks
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Part Number
Manufacturer
Quantity
Price
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5.1 Port P0 (P00 to P02)
bit in P0OUTCR to “0”.
for each bit in P0OUTCR.
state can be read from the P0PRD register.
Port P0 is a 3-bit input/output port that can also be used for external interrupt input or PPG output.
A reset initializes the output latch (P0DR) to “1” and the Pch control (P0OUTCR) to “0”.
To use a pin in Port P0 as an input port or external interrupt input, set P0DR to “1” and then set the corresponding
To use a pin in Port P0 as a PPG output, set P0DR to “1”.
The output circuit of Port P0 can be set either as sink open-drain output (“0”) or CMOS output (“1”) individually
Port P0 has a separate data input register. The output latch state can be read from the P0DR register, and the pin
Output latch read (P0DR)
Data input (P0PRD)
Data output (P0DR)
P0OUTCRi input
Control output
Control input
P0OUTCRi
Table 5-3 Register Programming for Port P0 (P00 to P02)
Port input, external interrupt input
Port "0" output
Port "1" output, PPG output
OUTEN
STOP
Output latch
Function
D
D
Figure 5-2 Port P0
Q
Q
Page 53
P0DR
“1”
“0”
“1”
Programmed Value
appropriate.
P0OUTCR
Set as
“0”
P0i
Note) i = 2~0
TMP86FS28DFG
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