TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 64

• Manufacturer Part Number: TMP86FS28DFG(JZ)
• Description: IC MCU 8BIT FLASH 60KB 80-LQFP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FS28DFG(JZ)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FS28DFGJZ

to externally hold input data until it is read externally or to read input data multiple times before it is processed. Fig-
ure 5-1 shows input/output timings.
timing cannot be recognized externally, transient input such as chattering must be processed by software. Data is out-
put to an input/output port in the S2 state of the write cycle in instruction execution.
Each output port contains a latch for holding output data. All input ports do not have latches, making it necessary
External data is read from an input/output port in the S1 state of the read cycle in instruction execution. Since this
Note: The positions of the read and write cycles may vary depending on the instruction.
Input strobe
Data input
Output latch pulse
Data output
Instruction
execution cycle
Instruction
execution cycle
Figure 5-1 Input/Output Timings (Example)
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Fetch cycle
Fetch cycle
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Ex: LD A, (x)
Ex: LD (x), A
(b) Output timing
(a) Input timing
Fetch cycle
Fetch cycle
Read cycle
Write cycle
TMP86FS28DFG