TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 190

• Manufacturer Part Number: TMP86FS28DFG(JZ)
• Description: IC MCU 8BIT FLASH 60KB 80-LQFP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FS28DFG(JZ)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FS28DFGJZ

13.9 Status Flag
13.9.4 Receive Data Buffer Full
13.9.5 Transmit Data Buffer Empty
RXD0 pin
RD0BUF
UART0SR<RBFL>
INTRXD0 interrupt
Shift register
UART0SR<RBFL> is cleared to “0” when the RD0BUF is read after reading the UART0SR.
shift register and data transmit starts, transmit data buffer empty flag UART0SR<TBEP> is set to “1”. The
UART0SR<TBEP> is cleared to “0” when the TD0BUF is written after reading the UART0SR.
UART0SR<RBFL>
RXD0 pin
RD0BUF
UART0SR<OERR>
INTRXD0 interrupt
Shift register
Note:Receive operations are disabled until the overrun error flag UART0SR<OERR> is cleared.
Loading the received data in RD0BUF sets receive data buffer full flag UART0SR<RBFL> to "1". The
Note:If the overrun error flag UART0SR<OERR> is set during the period between reading the UART0SR and read-
When no data is in the transmit buffer TD0BUF, that is, when data in TD0BUF are transferred to the transmit
ing the RD0BUF, it cannot be cleared by only reading the RD0BUF. Therefore, after reading the RD0BUF,
read the UART0SR again to check whether or not the overrun error flag which should have been cleared still
remains set.
Figure 13-8 Generation of Receive Data Buffer Full
Figure 13-7 Generation of Overrun Error
xxx0 **
yyyy
xxx0 **
yyyy
Final bit
Final bit
Page 178
xxxx0
xxxx0
*
*
Stop
Stop
1xxxx0
xxxx
1xxxx0
After reading UART0SR then
RD0BUF clears RBFL.
After reading UART0SR then
RD0BUF clears OERR.
TMP86FS28DFG