TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 189

• Manufacturer Part Number: TMP86FS28DFG(JZ)
• Description: IC MCU 8BIT FLASH 60KB 80-LQFP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FS28DFG(JZ)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FS28DFGJZ

13.9 Status Flag
13.9.1 Parity Error
13.9.2 Framing Error
13.9.3 Overrun Error
RXD0 pin
UART0SR<FERR>
INTRXD0 interrupt
UART0SR<PERR> is set to “1”. The UART0SR<PERR> is cleared to “0” when the RD0BUF is read after
reading the UART0SR.
The UART0SR<FERR> is cleared to “0” when the RD0BUF is read after reading the UART0SR.
Shift register
UART0SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD0BUF are not affected.
The UART0SR<OERR> is cleared to “0” when the RD0BUF is read after reading the UART0SR.
Shift register
RXD0 pin
UART0SR<PERR>
INTRXD0 interrupt
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
When “0” is sampled as the stop bit in the receive data, framing error flag UART0SR<FERR> is set to “1”.
When all bits in the next data are received while unread data are still in RD0BUF, overrun error flag
Figure 13-6 Generation of Framing Error
Figure 13-5 Generation of Parity Error
xxxx0 **
xxx0 **
Final bit
Parity
Page 177
pxxxx0
xxxx0
Stop
*
*
Stop
1pxxxx0
0xxxx0
After reading UART0SR then
RD0BUF clears FERR.
After reading UART0SR then
RD0BUF clears PERR.
TMP86FS28DFG