TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 188

• Manufacturer Part Number: TMP86FS28DFG(JZ)
• Description: IC MCU 8BIT FLASH 60KB 80-LQFP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FS28DFG(JZ)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FS28DFGJZ

13.6 STOP Bit Length
13.6 STOP Bit Length
13.7 Parity
13.8 Transmit/Receive Operation
13.8.1 Data Transmit Operation
13.8.2 Data Receive Operation
UART0CR1<EVEN>.
Select a transmit stop bit length (1 bit or 2 bits) by UART0CR1<STBT>.
Set parity / no parity by UART0CR1<PE> and set parity type (Odd- or Even-numbered) by
TD0BUF (Transmit data buffer). Writing data in TD0BUF zero-clears UART0SR<TBEP>, transfers the data
to the transmit shift register and the data are sequentially output from the TXD0 pin. The data output include a
one-bit start bit, stop bits whose number is specified in UART0CR1<STBT> and a parity bit if parity addition
is specified. Select the data transfer baud rate using UART0CR1<BRG>. When data transmit starts, transmit
buffer empty flag UART0SR<TBEP> is set to “1” and an INTTXD0 interrupt is generated.
written to TD0BUF, the TXD0 pin is fixed at high level.
When transmitting data, first read UART0SR, then write data in TD0BUF. Otherwise, UART0SR<TBEP> is
not zero-cleared and transmit does not start.
RD0BUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity
bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to
RD0BUF (Receive data buffer). Then the receive buffer full flag UART0SR<RBFL> is set and an INTRXD0
interrupt is generated. Select the data transfer baud rate using UART0CR1<BRG>.
data buffer) but discarded; data in the RD0BUF are not affected.
Set UART0CR1<TXE> to “1”. Read UART0SR to check UART0SR<TBEP> = “1”, then write data in
While UART0CR1<TXE> = “0” and from when “1” is written to UART0CR1<TXE> to when send data are
Set UART0CR1<RXE> to “1”. When data are received via the RXD0 pin, the receive data are transferred to
If an overrun error (OERR) occurs when data are received, the data are not transferred to RD0BUF (Receive
Note:When a receive operation is disabled by setting UART0CR1<RXE> bit to “0”, the setting becomes valid when
data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting
may not become valid. If a framing error occurs, be sure to perform a re-receive operation.
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TMP86FS28DFG