TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 179
TMP86FS28DFG(JZ)
Manufacturer Part Number
TMP86FS28DFG(JZ)
Description
IC MCU 8BIT FLASH 60KB 80-LQFP
Manufacturer
Toshiba
Series
TLCS-870/Cr
Datasheet
1.TMP86FS28DFGJZ.pdf
(272 pages)
Specifications of TMP86FS28DFG(JZ)
Core Processor
870/C
Core Size
8-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LCD, PWM, WDT
Number Of I /o
62
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Processor Series
TLCS-870
Core
870/C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SIO, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
62
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
TMP86FS28DFGJZ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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12.9 Status Flag
12.9.1 Parity Error
12.9.2 Framing Error
12.9.3 Overrun Error
RXD1 pin
UART1SR<FERR>
INTRXD1 interrupt
UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the RD1BUF is read after
reading the UART1SR.
The UART1SR<FERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR.
Shift register
UART1SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD1BUF are not affected.
The UART1SR<OERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR.
Shift register
RXD1 pin
UART1SR<PERR>
INTRXD1 interrupt
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
When “0” is sampled as the stop bit in the receive data, framing error flag UART1SR<FERR> is set to “1”.
When all bits in the next data are received while unread data are still in RD1BUF, overrun error flag
Figure 12-6 Generation of Framing Error
Figure 12-5 Generation of Parity Error
xxxx0 **
xxx0 **
Final bit
Parity
Page 167
pxxxx0
xxxx0
Stop
*
*
Stop
1pxxxx0
0xxxx0
After reading UART1SR then
RD1BUF clears FERR.
After reading UART1SR then
RD1BUF clears PERR.
TMP86FS28DFG
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