TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet
TMP86FS28DFG(JZ)
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Bit Microcontroller TLCS-870/C Series TMP86FS28DFG ...
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... It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “ ...
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Date Revision 2006/4/8 1 2006/6/29 2 2006/9/28 3 2007/7/24 4 Revision History First Release Periodical updating.No change in contents. Contents Revised Contents Revised ...
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...
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Table of Contents TMP86FS28DFG 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Undefined Instruction Interrupt (INTUNDEF 3.6 Address Trap Interrupt (INTATRAP) . ...
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Configuration .......................................................................................................................................... 83 8.1.2 TimerCounter Control ............................................................................................................................. 84 8.1.3 Function .................................................................................................................................................. 85 8.1.3.1 Timer mode 8.1.3.2 External Trigger Timer Mode 8.1.3.3 Event Counter Mode 8.1.3.4 Window Mode 8.1.3.5 Pulse Width Measurement Mode 8.1.3.6 Programmable Pulse Generate (PPG) Output Mode ...
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Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AD Converter (ADC) 14.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Flash Memory Control in the Serial PROM Mode............................................................................... 215 17.4.2 Flash Memory Control in the MCU mode............................................................................................ 216 17.4.2.1 How to write to the flash memory by executing a user write control program in the RAM area (in the ...
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Recommended Oscillating Conditions 255 20.8 Handling Precaution . ...
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viii ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C • ...
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Features Programmable pulse generation (PPG) modes 8. 8-bit UART/SIO 8-bit UART : 1 ch 10. 10-bit successive approximation type AD converter - Analog input 11. Key-on wakeup : 4 ch 12. LCD driver/controller Built-in ...
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Pin Assignment (SEG10) P75 (SEG9) P76 (SEG8) P77 (SEG7) P80 (SEG6) P81 (SEG5) P82 (SEG4) P83 (SEG3) P84 (SEG2) P85 (SEG1) P86 (SEG0) P87 COM3 COM2 COM1 COM0 ...
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Block Diagram 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86FS28DFG ...
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Pin Names and Functions The TMP86FS28DFG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin ...
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Pin Names and Functions Table 1-1 Pin Names and Functions(2/4) Pin Name P33 P32 P31 DVO P30 INT0 P47 SEG32 P46 SEG33 P45 SEG34 P44 SEG35 P43 SEG36 TC11 P42 SEG37 PPG11 P41 SEG38 INT2 P40 SEG39 INT1 P57 ...
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Table 1-1 Pin Names and Functions(3/4) Pin Name Pin Number P50 SEG31 40 TXD0 P67 55 SEG16 P66 54 SEG17 P65 53 SEG18 P64 52 SEG19 P63 51 SEG20 P62 50 SEG21 P61 49 SEG22 P60 48 SEG23 P77 63 ...
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Pin Names and Functions Table 1-1 Pin Names and Functions(4/4) Pin Name P81 SEG6 P80 SEG7 COM3 COM2 COM1 COM0 XIN XOUT RESET TEST VAREF AVDD AVSS VDD VSS Pin Number Input/Output IO 65 ...
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Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset ...
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System Clock Controller The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to “00H”. (TMP86FS28DFG) SRAMCLR: 2.2 System Clock Controller The ...
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High-frequency clock XIN XOUT XIN (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog ...
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System Clock Controller 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of ...
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Timing Generator Control Register TBTCR (0036H) (DVOEN) (DVOCK) Selection of input to the 7th stage DV7CK of the divider Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” ...
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System Clock Controller (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> ...
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Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. ...
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System Clock Controller IDLE1 mode (a) Single-clock mode IDLE2 mode SLEEP2 mode SLEEP1 mode (b) Dual-clock mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called ...
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System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN STOP STOP mode start Release method for STOP RELM mode Operating mode after STOP RETM mode OUTEN Port output during STOP mode Warm-up time at releasing WUT ...
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System Clock Controller 2.2.4 Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). The pin is also ...
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Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 JRS F, SINT5 LD (SYSCR1), 01010000B DI SET (SYSCR1). 7 SINT5: RETI STOP pin XOUT pin NORMAL operation Confirm by program that the STOP ...
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System Clock Controller STOP mode is released by the following sequence the dual-clock mode, when returning to NORMAL2, both the high-frequency and low warm-up period is inserted to allow oscillation time to stabilize. During warm ...
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Figure 2-9 STOP Mode Start/Release Page 21 TMP86FS28DFG ...
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System Clock Controller 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and ...
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Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 ...
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System Clock Controller Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24 TMP86FS28DFG ...
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IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing ...
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System Clock Controller • Start the IDLE0 and SLEEP0 modes • Release the IDLE0 and SLEEP0 modes of TBT and TBTCR<TBTEN>. cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before ...
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Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27 TMP86FS28DFG ...
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System Clock Controller 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, ...
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Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the main system clock to the ...
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System Clock Controller Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30 TMP86FS28DFG ...
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Reset Circuit The TMP86FS28DFG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and ...
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Reset Circuit 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or ...
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Page 33 TMP86FS28DFG ...
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Reset Circuit Page 34 TMP86FS28DFG ...
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Interrupt Control Circuit The TMP86FS28DFG has a total of 23 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt ...
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Interrupt latches (IL29 to IL2) 3.1 Interrupt latches (IL29 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. When interrupt request is generated, the ...
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Individual interrupt enable flags (EF29 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting ...
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Interrupt enable register (EIR) Interrupt Latches 15 14 ILH,ILL (003DH, 003CH) IL15 IL14 15 14 ILD,ILE (002FH, 002EH) IL31 IL30 IL29 to IL2 Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" ...
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Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after ...
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Interrupt Sequence A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF ...
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Example :Save/store register using data transfer instructions PINTxx: LD (interrupt processing) LD RETI Main task Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as ...
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Software Interrupt (INTSW) Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter- rupt ...
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External Interrupts The TMP86FS28DFG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. ...
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External Interrupts External Interrupt Control Register EINTCR 7 (0037H) INT1NC INT0EN INT1NC INT0EN INT4 ES INT3 ES INT2 ES INT1 ES Note 1: fc: High-frequency clock [Hz], *: Don’t care Note 2: When the system clock frequency is switched ...
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Special Function Register (SFR) The TMP86FS28DFG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address ...
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SFR Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Note 1: Do not access reserved areas by the program. Note ...
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DBR Address 0F00H : : 0F5FH Address 0F60H 0F61H 0F62H 0F63H 0F64H 0F65H 0F66H 0F67H 0F68H 0F69H Address 0F70H : : 0F7FH Read Write Reserved : : Reserved Read Write SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 - ...
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DBR Address 0F80H 0F9FH Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H 0FB7H 0FB8H 0FB9H 0FBAH 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH Read : ...
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Address Read 0FC0H 0FC1H 0FC2H 0FC3H 0FC4H 0FC5H 0FC6H 0FC7H 0FC8H 0FC9H 0FCAH 0FCBH 0FCCH 0FCDH 0FCEH 0FCFH 0FD0H 0FD1H 0FD2H 0FD3H 0FD4H 0FD5H 0FD6H 0FD7H 0FD8H 0FD9H 0FDAH 0FDBH 0FDCH 0FDDH 0FDEH 0FDFH Page 49 TMP86FS28DFG Write SEG1/0 SEG3/2 ...
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DBR Address 0FE0H 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H 0FF1H 0FF2H 0FF3H 0FF4H 0FF5H 0FF6H 0FF7H 0FF8H 0FF9H 0FFAH 0FFBH 0FFCH 0FFDH 0FFEH 0FFFH Note 1: Do not access ...
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I/O Ports The TMP86FS28DFG has 9 input/output ports (62 pins) as shown below. Port Functions Table 5-1 Primary Function Port P0 3-bit input/output port Port P1 8-bit input/output port Port P2 3-bit input/output port Port P3 8-bit input/output port ...
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Each output port contains a latch for holding output data. All input ports do not have latches, making it necessary to externally hold input data until it is read externally or to read input data multiple times before it is ...
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Port P0 (P00 to P02) Port 3-bit input/output port that can also be used for external interrupt input or PPG output. A reset initializes the output latch (P0DR) to “1” and the Pch control (P0OUTCR) to ...
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Port P0 (P00 to P02 P0DR (0000H) R/W P0OUTCR 7 6 (0032H) R/W Port P0 input/output control P0OUTCR (set for each bit individually P0PRD (0FF0H) Read only P02 P01 PPG1 ...
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Port P1 (P10 to P17) Port 8-bit input/output port that can be configured as an input or an output on a bit basis. Port P1 is also used for analog input or key-on wake-up input. The ...
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Port P1 (P10 to P17) Analog input AINDS SAIN P CR2i P1CR2i input P1CR1i P1CR1i input Data input (P1DR) Data output (P1DR) STOP OUTEN STOPk Key-on wake-up Analog input AINDS SAIN P1CR2j P1CR2j input P1CR1j P1CR1j input Data input ...
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P1DR P17 P16 P15 P14 (0001H) AIN7 AIN6 AIN5 AIN4 R/W STOP5 STOP4 P1CR1 (0FF9H) Port P1 input/output control P1CR1 (set for each bit individually P1CR2 (0FFAH) Port P1 input control ...
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Port P2 (P20 to P22) 5.3 Port P2 (P20 to P22) Port 3-bit input/output port that can also be used for external interrupt input, STOP mode release signal input, or low-frequency resonator connection. To use Port ...
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Port P3 (P30 to P37) Port 8-bit input/output port that can also be used for external interrupt input, divider output, timer/counter input, serial interface input/output, or UART input/output. A reset initializes the output latch (P3DR) to ...
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Port P3 (P30 to P37 P3DR P37 P36 (0003H) TC10 SCK R/W INT4 7 6 P3OUTCR (002BH) Port P3 output circuit control P3OUTCR (set for each bit individually P3PRD (0FF3H) P37 P36 Read only 5 ...
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Port P4 (P40 to P47) Port 8-bit input/output port that can also be used for external interrupt input, PPG output, timer/counter input, or LCD segment output. A reset initializes the output latch (P4DR) to “1”, the ...
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Port P4 (P40 to P47 P4DR P47 P46 (0004H) SEG32 SEG31 R P4LCR (0FD4H) Port P4 segment output control P4LCR (Set for each bit individually P4OUTCR (0FFBH) P4 output circuit control P4OUTCR (Set ...
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Port P5 (P50 to P57) Port 8-bit input/output port that can also be used for timer/counter input/output, LCD segment output, or UART input/output. A reset initializes the output latch (P5DR) to “1”, the Pch control (P5OUTCR) ...
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Port P5 (P50 to P57 P57 P56 P5DR SEG24 SEG25 (0005H) R P5LCR (0FD5H) Port P5 segment output control P5LCR (Set for each bit individually P5OUTCR (0FFCH) Port P5 input/output control P5OUTCR (Set ...
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Port P6 (P60 to P67) Port 8-bit input/output port that can also be used for LCD segment output. A reset initializes the output latch (P6DR) to “1”, the Pch control (P6OUTCR) to “0”, and the LCD ...
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Port P6 (P60 to P67 P6DR (0006H) P67 P66 R/W SEG16 SEG17 7 6 P6LCR (0FD6H) Port P6 segment output control P6LCR (Set for each bit individually P6OUTCR (0FFDH) Port P6 input/output control P6CR2 (Set ...
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Port P7 (P70 to P77) Port 8-bit input/output port that can also be used for LCD segment output. A reset initializes the output latch (P7DR) to “1”, the Pch control (P7OUTCR) to “0”, and the LCD ...
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Port P7 (P70 to P77 P7DR (0007H) P77 P76 R/W SEG8 SEG9 7 6 P7LCR (0FD7H) Port P7 segment output control P7LCR (set for each bit individually P7OUTCR (0FFEH) Port P7 input/output control P7OUTCR (set ...
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Port P8 (P80 to P87) Port 8-bit input/output port that can also be used for LCD segment output. A reset initializes the output latch (P8DR) to “1”, the Pch control (P8OUTCR) to “0”, and the LCD ...
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Port P8 (P80 to P87 P8DR (0008H) P87 P86 R/W SEG0 SEG1 7 6 P8LCR (0FD8H) Port P8 segment output control P8LCR (Set for each bit individually P8OUTCR (0FFFH) Port P8 input/output control P8OUTCR (Set ...
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Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The ...
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Watchdog Timer Control 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog ...
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Watchdog Timer Control Register WDTCR1 (0034H) (ATAS) WDTEN Watchdog timer enable/disable Watchdog timer detection time WDTT [s] WDTOUT Watchdog timer output select Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”. ...
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Watchdog Timer Control 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master ...
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Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is maximum ...
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Address Trap 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register WDTCR1 (0034H) Select address trap generation in ATAS ...
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Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the ...
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Address Trap Page 78 TMP86FS28DFG ...
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Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration MPX 23 15 fc/2 or fs/2 21 ...
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Time Base Timer Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling ...
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Divider Output ( DVO Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from 7.2.1 Configuration Output latch D Q Data output MPX ...
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Divider Output (DVO) Example :1.95 kHz pulse output (fc = 16.0 MHz) Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz 32.768 kHz ) DVOCK LD (TBTCR) , 00000000B LD (TBTCR) , 10000000B Divider ...
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TimerCounter (TC10,TC11) 16-Bit TimerCounter 10 8.1 8.1.1 Configuration Figure 8-1 TimerCounter 10 (TC10) Page 83 TMP86FS28DFG ...
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TimerCounter 10 8.1.2 TimerCounter Control The TimerCounter 10 is controlled by the TimerCounter 10 control register (TC10CR) and two 16-bit timer registers (TC10DRA and TC10DRB). Timer Register 15 14 TC10DRA (0011H, 0010H) TC10DRB (0013H, 0012H) TimerCounter 10 Control ...
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Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC10DRA > TC10DRB > 1 (PPG output mode), TC10DRA > 1 (other ...
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TimerCounter 10 Example 2 :Auto-capture Note: Since the up-counter value is captured into TC10DRB by the source clock of up-counter after setting TC10CR<ACAP10> to "1". Therefore, to read the captured value, wait at least one ...
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External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC10 pin, and counts up at the edge of the internal clock. For the trigger edge used to ...
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TimerCounter 10 Count start TC10 pin input Source clock Up-counter 0 TC10DRA INTTC10 interrupt request Count start TC10 pin input Source clock Up-counter 0 1 TC10DRA INTTC10 interrupt request Figure 8-3 External Trigger Timer Mode Timing Chart n ...
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Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC10 pin. Either the rising or falling edge of the input pulse is selected as the count up ...
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TimerCounter 10 8.1.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC10 pin (window pulse) and the internal ...
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Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC10 pin, and counts up at the edge of the internal clock. Either the rising or falling edge ...
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TimerCounter 10 Example :Duty measurement (resolution fc/2 PINTTC10: SINTTC10: VINTTC10: TC10 pin INTTC10 interrupt request INTTC10SW 7 [Hz]) CLR (INTTC10SW INTTC10 service switch initial setting Address set to convert INTTC10SW at each INTTC10 LD (TC10CR), 00000110B ...
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Count start TC10 pin input Trigger Internal clock Counter 0 1 TC10DRB INTTC10 interrupt request Count start TC10 pin input Internal clock Counter 0 1 TC10DRB INTTC10 interrupt request Figure 8-6 Pulse Width Measurement Mode ...
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TimerCounter 10 8.1.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC10CR<TC10S> specifies either the edge ...
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Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs ( MHz) Setting port LD (TC10CR), 10000111B LDW (TC10DRA), 007DH LDW (TC10DRB), 0019H LD (TC10CR), 10010111B Example :After stopping PPG, setting the PPG ...
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TimerCounter 10 Internal clock Counter TC10DRB TC10DRA PPG pin output INTTC10 interrupt request TC10 pin input Internal clock Counter TC10DRB TC10DRA PPG pin output INTTC10 interrupt request Timer start ...
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TimerCounter 11 8.2 8.2.1 Configuration Figure 8-9 TimerCounter 11 (TC11) Page 97 TMP86FS28DFG ...
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TimerCounter 11 8.2.2 TimerCounter Control The TimerCounter 11 is controlled by the TimerCounter 11 control register (TC11CR) and two 16-bit timer registers (TC11DRA and TC11DRB). Timer Register 15 14 TC11DRA (0021H, 0020H) TC11DRB (0023H, 0022H) TimerCounter 11 Control ...
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Writing only the lower byte (TC11DRAL and TC11DRBL) does not enable the setting of the timer register. Note 3: To ...
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TimerCounter 11 Example 1 :Setting the timer mode with source clock fc/2 ( MHz, TBTCR<DV7CK> = “0”) LDW DI SET Example 2 :Auto-capture Note: Since the up-counter value is captured ...
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External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC11 pin, and counts up at the edge of the internal clock. For the trigger edge used to ...
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TimerCounter 11 Count start TC11 pin input Source clock Up-counter 0 TC11DRA INTTC11 interrupt request Count start TC11 pin input Source clock Up-counter 0 1 TC11DRA INTTC11 interrupt request Figure 8-11 External Trigger Timer Mode Timing Chart n ...
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Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC11 pin. Either the rising or falling edge of the input pulse is selected as the count up ...
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TimerCounter 11 8.2.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC11 pin (window pulse) and the internal ...
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Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC11 pin, and counts up at the edge of the internal clock. Either the rising or falling edge ...
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TimerCounter 11 Example :Duty measurement (resolution fc/2 PINTTC11: SINTTC11: VINTTC11: TC11 pin INTTC11 interrupt request INTTC11SW 7 [Hz]) CLR (INTTC11SW INTTC11 service switch initial setting Address set to convert INTTC11SW at each INTTC11 LD (TC11CR), 00000110B ...
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Count start TC11 pin input Trigger Internal clock Counter TC11DRB INTTC11 interrupt request Count start TC11 pin input Internal clock Counter TC11DRB INTTC11 interrupt request Figure 8-14 Pulse Width Measurement Mode ...
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TimerCounter 11 8.2.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC11CR<TC11S> specifies either the edge ...
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Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs ( MHz) Setting port LD (TC11CR), 10000111B LDW (TC11DRA), 007DH LDW (TC11DRB), 0019H LD (TC11CR), 10010111B Example :After stopping PPG, setting the PPG ...
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TimerCounter 11 Internal clock Counter TC11DRB TC11DRA PPG pin output INTTC11 interrupt request TC11 pin input Internal clock Counter TC11DRB TC11DRA PPG pin output INTTC11 interrupt request Timer start ...
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TimerCounter (TC3, TC4) 9.1 Configuration 11 3 fc fc/2 16-bit mode G fc TC4 pin H S TC4M ...
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Configuration 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 7 6 (0015H) R/W PWREG3 7 6 (0019H) R/W Note 1: ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the ...
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Configuration The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 7 6 (0016H) R/W PWREG4 7 6 (001AH) R/W Note 1: Do not ...
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Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending ...
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Configuration Table 9-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- ...
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Configuration TC4CR<TC4S> Internal Source Clock Counter TTREG4 ? INTTC4 interrupt request 9.3.2 8-Bit Event Counter Mode (TC3 the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj ...
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Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift ...
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Configuration Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Page 120 TMP86FS28DFG ...
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Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up-counter counts up using the internal clock. When a match between ...
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Configuration Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) Page 122 TMP86FS28DFG ...
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Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the ...
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Configuration 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. ...
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CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, ...
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Configuration Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 126 TMP86FS28DFG ...
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Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The ...
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Configuration Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC4) Page 128 TMP86FS28DFG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit ...
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Configuration 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, ...
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TimerCounter (TC5, TC6) 10.1 Configuration 11 3 fc fc/2 16-bit mode G fc TC6 pin H S TC6M ...
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Configuration 10.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 7 6 (0017H) R/W PWREG5 7 6 (001BH) R/W Note 1: ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 10- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the ...
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Configuration The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 7 6 (0018H) R/W PWREG6 7 6 (001CH) R/W Note 1: Do not ...
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Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR<TC5CK>. Set the timer start control and timer F/F control by programming TC6S and TFF6, respectively. Note 7: The operating clock settings are limited depending ...
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Configuration Table 10-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16- ...
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Configuration TC6CR<TC6S> Internal Source Clock Counter TTREG6 ? INTTC6 interrupt request Figure 10-2 8-Bit Timer Mode Timing Chart (TC6) 10.3.2 8-Bit Event Counter Mode (TC5 the 8-bit event counter mode, the up-counter counts up at the falling ...
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Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift ...
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Configuration Figure 10-4 8-Bit PDO Mode Timing Chart (TC6) Page 140 TMP86FS28DFG ...
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Pulse Width Modulation (PWM) Output Mode (TC5, 6) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up-counter counts up using the internal clock. When a match between ...
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Configuration Figure 10-5 8-Bit PWM Mode Timing Chart (TC6) Page 142 TMP86FS28DFG ...
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Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascad- able to form a 16-bit timer. When a match between the up-counter and the ...
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Configuration 10.3.6 16-Bit Event Counter Mode (TC5 and 6) In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5 and 6 are cascadable to form a 16-bit event counter. ...
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CLR (TC6CR).3: Stops the timer. CLR (TC6CR).7 : Sets the Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, ...
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Configuration Figure 10-7 16-Bit PWM Mode Timing Chart (TC5 and TC6) Page 146 TMP86FS28DFG ...
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Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascad- able to enter the 16-bit PPG mode. The ...
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Configuration Figure 10-8 16-Bit PPG Mode Timing Chart (TC5 and TC6) Page 148 TMP86FS28DFG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a 16-bit ...
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Configuration 10.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, ...
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Synchronous Serial Interface (SIO) The TMP86FS28DFG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer bits of data. Serial interface is connected to ...
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Control 11.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2<BUF>. The data ...
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WAIT Wait control Number of transfer words BUF (Buffer address in use) Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts ...
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Serial clock 11.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) ...
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Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 11.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the output). 11.3.2.2 Trailing ...
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Transfer Mode SCK pin SO pin INTSIO interrupt SCK pin SO pin INTSIO interrupt SCK pin SI pin INTSIO interrupt Figure 11-6 Number of words to transfer (Example: 1word = 4bit) 11.6 Transfer Mode SIOCR1<SIOM> is used to select ...
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SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted. That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF> is cleared to “0” when a transfer is completed. When SIOCR1<SIOINH> ...
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Transfer Mode SCK pin SIOSR<SIOF> SO pin Figure 11-9 Transmiiied Data Hold Time at End of Transfer 11.6.2 4-bit and 8-bit receive modes After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. ...
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SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin (Output) SI pin INTSIO Interrupt DBR Figure 11-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock) 11.6.3 8-bit transfer / receive mode After setting the SIO control register to the 8-bit ...
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Transfer Mode Note:The buffer contents are lost when the transfer mode is switched should become necessary to switch the transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the trans- ...
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Asynchronous Serial interface (UART1 ) 12.1 Configuration UART control register 1 UART1CR1 3 2 INTTXD1 INTRXD1 S fc/ fc/26 C fc/52 fc/104 fc/208 fc/416 F INTTC5 G H fc/96 Baud rate generator Figure 12-1 ...
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Control 12.2 Control UART1 is controlled by the UART1 Control Registers (UART1CR1, UART1CR2). The operating status can be monitored using the UART status register (UART1SR). UART1 Control Register1 7 6 UART1CR1 (0FE8H) TXE RXE TXE Transfer operation RXE Receive ...
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UART1 Status Register UART1SR (0FE8H) PERR FERR OERR RBFL PERR Parity error flag FERR Framing error flag OERR Overrun error flag RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty ...
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Transfer Data Format 12.3 Transfer Data Format In UART1, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART1CR1<STBT>), and parity (Select parity in UART1CR1<PE>; even- or odd-numbered parity by UART1CR1<EVEN>) are added ...
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Transfer Rate The baud rate of UART1 is set of UART1CR1<BRG>. The example of the baud rate are shown as follows. Table 12-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC5 is used as the ...
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STOP Bit Length 12.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART1CR1<STBT>. 12.7 Parity Set parity / no parity by UART1CR1<PE> and set parity type (Odd- or Even-numbered) by UART1CR1<EVEN>. 12.8 ...
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Status Flag 12.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the RD1BUF is read ...
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Status Flag UART1SR<RBFL> RXD1 pin Shift register RD1BUF UART1SR<OERR> INTRXD1 interrupt Note:Receive operations are disabled until the overrun error flag UART1SR<OERR> is cleared. 12.9.4 Receive Data Buffer Full Loading the received data in RD1BUF sets receive data buffer full ...
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TD1BUF xxxx ***** 1 1xxxx0 Shift register TXD1 pin Start UART1SR<TBEP> INTTXD1 interrupt Figure 12-9 Generation of Transmit Data Buffer Empty 12.9.6 Transmit End Flag When data are transmitted and no data is in TD1BUF (UART1SR<TBEP> = “1”), transmit end ...
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Status Flag Page 170 TMP86FS28DFG ...
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Asynchronous Serial interface (UART0 ) 13.1 Configuration UART control register 1 UART0CR1 3 2 INTTXD0 INTRXD0 S fc/ fc/26 C fc/52 fc/104 fc/208 fc/416 F INTTC3 G H fc/96 Baud rate generator Figure 13-1 ...
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Control 13.2 Control UART0 is controlled by the UART0 Control Registers (UART0CR1, UART0CR2). The operating status can be monitored using the UART status register (UART0SR). UART0 Control Register1 7 6 UART0CR1 (0FE5H) TXE RXE TXE Transfer operation RXE Receive ...
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UART0 Status Register UART0SR (0FE5H) PERR FERR OERR RBFL PERR Parity error flag FERR Framing error flag OERR Overrun error flag RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty ...
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Transfer Data Format 13.3 Transfer Data Format In UART0, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART0CR1<STBT>), and parity (Select parity in UART0CR1<PE>; even- or odd-numbered parity by UART0CR1<EVEN>) are added ...
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Transfer Rate The baud rate of UART0 is set of UART0CR1<BRG>. The example of the baud rate are shown as follows. Table 13-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC3 is used as the ...
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STOP Bit Length 13.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART0CR1<STBT>. 13.7 Parity Set parity / no parity by UART0CR1<PE> and set parity type (Odd- or Even-numbered) by UART0CR1<EVEN>. 13.8 ...
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Status Flag 13.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART0SR<PERR> is set to “1”. The UART0SR<PERR> is cleared to “0” when the RD0BUF is read ...
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Status Flag UART0SR<RBFL> RXD0 pin Shift register RD0BUF UART0SR<OERR> INTRXD0 interrupt Note:Receive operations are disabled until the overrun error flag UART0SR<OERR> is cleared. 13.9.4 Receive Data Buffer Full Loading the received data in RD0BUF sets receive data buffer full ...
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TD0BUF xxxx ***** 1 1xxxx0 Shift register TXD0 pin Start UART0SR<TBEP> INTTXD0 interrupt Figure 13-9 Generation of Transmit Data Buffer Empty 13.9.6 Transmit End Flag When data are transmitted and no data is in TD0BUF (UART0SR<TBEP> = “1”), transmit end ...
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Status Flag Page 180 TMP86FS28DFG ...
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AD Converter (ADC) The TMP86FS28DFG have a 10-bit successive approximation type AD converter. 14.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 14-1. It consists of control register ADCCR1 and ADCCR2, converted value ...
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Register configuration 14.2 Register configuration The AD converter consists of the following four registers converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to per- form ...
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AD Converter Control Register ADCCR2 (0FE3H) IREFON DA converter (Ladder resistor) connection IREFON control AD conversion time select ACK (Refer to the following table about the con- version time) Note 1: Always set bit0 in ADCCR2 ...
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Register configuration EOCF ADBF Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: The ADCDR2<ADBF> is set to "1" when ...
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Function 14.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD ...
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Function ADCCR1<AMD> AD conversion start ADCCR1<ADRS> Conversion operation Indeterminate ADCDR1,ADCDR2 ADCDR2<EOCF> INTADC interrupt request ADCDR1 ADCDR2 14.3.3 Register Setting 1. Set up the AD converter control register 1 (ADCCR1) as follows: • Choose the channel to AD convert using ...
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Example :After selecting the conversion time 19.5 µ MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store ...
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Analog Input Voltage and AD Conversion Result 14.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 14-4. 3FF H 3FE H ...