C8051T630-GM Silicon Laboratories Inc, C8051T630-GM Datasheet
C8051T630-GM
Specifications of C8051T630-GM
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C8051T630-GM Summary of contents
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... C8051T630/1/2/3/4/5 Timer 3 supports real-time clock using external clock source 24.5 MHz with ±2% accuracy supports crystal-less UART operation and low-power suspend mode with fast wake time 80/40/20/10 kHz low frequency, low power operation Port 0 Port 1 P2.0 768 B SRAM POR WDT C8051T630/1/2/3/4/5 ...
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... C8051T630/1/2/3/4/5 2 Rev. 1.0 ...
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... Window Detector Example........................................................................ 42 6.5. ADC0 Analog Multiplexer (C8051T630/2/4 only)............................................... 43 7. Temperature Sensor (C8051T630/2/4 only) ........................................................... 45 7.1. Calibration ......................................................................................................... 45 8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only) ......................................... 48 8.1. IDA0 Output Scheduling .................................................................................... 48 8.1.1. Update Output On-Demand ...................................................................... 48 8.1.2. Update Output Based on Timer Overflow ................................................. 49 8.1.3. Update Output Based on CNVSTR Edge ................................................. 49 8 ...
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... C8051T630/1/2/3/4/5 15. Interrupts ................................................................................................................ 80 15.1. MCU Interrupt Sources and Vectors................................................................ 81 15.1.1. Interrupt Priorities.................................................................................... 81 15.1.2. Interrupt Latency ..................................................................................... 81 15.2. Interrupt Register Descriptions ........................................................................ 82 15.3. INT0 and INT1 External Interrupts................................................................... 87 16. EPROM Memory ..................................................................................................... 89 16.1. Programming and Reading the EPROM Memory ........................................... 89 16.1.1. EPROM Write Procedure ........................................................................ 89 16.1.2. EPROM Read Procedure........................................................................ 90 16 ...
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... Slave Select (NSS) ............................................................................... 157 23.2. SPI0 Master Mode Operation ........................................................................ 158 23.3. SPI0 Slave Mode Operation .......................................................................... 159 23.4. SPI0 Interrupt Sources .................................................................................. 160 23.5. Serial Clock Phase and Polarity .................................................................... 160 23.6. SPI Special Function Registers ..................................................................... 162 24. Timers ................................................................................................................... 169 24.1. Timer 0 and Timer 1 ...................................................................................... 171 C8051T630/1/2/3/4/5 Rev. 1.0 5 ...
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... C8051T630/1/2/3/4/5 24.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 171 24.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 172 24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 173 24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 174 24.2. Timer 2 .......................................................................................................... 179 24.2.1. 16-bit Timer with Auto-Reload............................................................... 179 24.2.2. 8-bit Timers with Auto-Reload............................................................... 180 24 ...
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... Temperature Sensor (C8051T630/2/4 only) Figure 7.1. Temperature Sensor Transfer Function ................................................ 45 Figure 7.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius ........... 46 8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only) Figure 8.1. IDA0 Functional Block Diagram ............................................................ 48 Figure 8.2. IDA0 Data Word Mapping ..................................................................... 49 9. Voltage Reference Options Figure 9 ...
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... C8051T630/1/2/3/4/5 Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 115 21. SMBus Figure 21.1. SMBus Block Diagram ...................................................................... 127 Figure 21.2. Typical SMBus Configuration ............................................................ 128 Figure 21.3. SMBus Transaction ........................................................................... 129 Figure 21.4. Typical SMBus SCL Generation ........................................................ 131 Figure 21.5. Typical Master Write Sequence ........................................................ 140 Figure 21 ...
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... Figure 25.8. PCA 8-Bit PWM Mode Diagram ........................................................ 199 Figure 25.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 200 Figure 25.10. PCA 16-Bit PWM Mode ................................................................... 201 Figure 25.11. PCA Module 2 with Watchdog Timer Enabled ................................ 202 26. C2 Interface Figure 26.1. Typical C2 Pin Sharing ...................................................................... 217 C8051T630/1/2/3/4/5 Rev. 1.0 9 ...
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... C8051T630/1/2/3/4/5 List of Tables 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 17 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5 ........................................... 18 4. QFN-20 Package Specifications Table 4.1. QFN-20 Package Dimensions ................................................................ 21 Table 4.2. QFN-20 PCB Land Pattern Dimesions ................................................... 22 5. Electrical Characteristics Table 5.1. Absolute Maximum Ratings .................................................................... 23 Table 5 ...
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... Enhanced Serial Peripheral Interface (SPI0) Table 23.1. SPI Slave Timing Parameters ............................................................ 168 25. Programmable Counter Array Table 25.1. PCA Timebase Input Options ............................................................. 192 Table 25.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules ................................................... 194 Table 25.3. Watchdog Timer Timeout Intervals1 ................................................... 203 C8051T630/1/2/3/4/5 Rev. 1.0 11 ...
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... C8051T630/1/2/3/4/5 List of Registers SFR Definition 6.1. ADC0CF: ADC0 Configuration ...................................................... 37 SFR Definition 6.2. ADC0H: ADC0 Data Word MSB .................................................... 38 SFR Definition 6.3. ADC0L: ADC0 Data Word LSB ...................................................... 38 SFR Definition 6.4. ADC0CN: ADC0 Control ................................................................ 39 SFR Definition 6.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 40 SFR Definition 6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 40 SFR Definition 6 ...
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... SFR Definition 25.1. PCA0CN: PCA Control .............................................................. 204 SFR Definition 25.2. PCA0MD: PCA Mode ................................................................ 205 SFR Definition 25.3. PCA0PWM: PCA PWM Configuration ....................................... 206 SFR Definition 25.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 207 SFR Definition 25.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 208 C8051T630/1/2/3/4/5 Rev. 1.0 13 ...
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... C8051T630/1/2/3/4/5 SFR Definition 25.6. PCA0H: PCA Counter/Timer High Byte ..................................... 208 SFR Definition 25.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 209 SFR Definition 25.8. PCA0CPHn: PCA Capture Module High Byte ........................... 209 C2 Register Definition 26.1. C2ADD: C2 Address ...................................................... 210 C2 Register Definition 26.2. DEVICEID: C2 Device ID ............................................... 211 C2 Register Definition 26 ...
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... Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An internal LDO is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are tolerant of input signals The C8051T630/1/2/3/4/5 are available in 20-pin QFN RoHS compliant packag- ing. See Table 2.1 for ordering information. A block diagram is shown in Figure 1.1. ...
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... Peripheral Power VDD Regulator Core Power GND Precision 24.5 MHz Oscillator Low-Freq. Oscillator External EXTCLK Oscillator Circuit System Clock Configuration Figure 1.1. C8051T630/1/2/3/4/5 Block Diagram 16 Port I/O Configuration Digital Peripherals UART Timers Priority Crossbar PCA/ Decoder WDT SMBus SPI SYSCLK Crossbar Control ...
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... Ordering Information Table 2.1. Product Selection Guide C8051T630-GM 25 8k* 768 Y C8051T631-GM 25 8k* 768 Y C8051T632- 768 Y C8051T633- 768 Y C8051T634- 768 Y C8051T635- 768 Y * 512 Bytes Reserved for Factory Use C8051T630/1/2/3/4 — — — — — — — — — — — — Rev. 1.0 ...
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... C8051T630/1/2/3/4/5 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5 Name Pin Type Description V 3 Power Supply Voltage. DD GND 2 Ground. RST I/O Device Reset. Open-drain output of internal POR or V external source can initiate a system reset by driving this pin low for at least 10 µs. ...
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... Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5 (Continued) Name Pin Type Description P0 I/O or Port 0. P1 I/O or Port 1. P1 I/O or Port 1. P1 I/O or Port 1. P1 I/O or Port 1. P1 I/O or Port 1. P1 I/O or Port 1. P1 I/O or Port 1. P1 I/O or Port 1. C8051T630/1/2/3/4/5 Rev. 1.0 ...
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... C8051T630/1/2/3/4/5 P0.0 1 GND 2 VDD 3 RST/C2CK 4 P2.0/C2D 5 Figure 3.1. QFN-20 Pinout Diagram (Top View) 20 C8051T630/1/2/3/4/5 Top View GND Rev. 1.0 P0.6/ 15 CNVSTR 14 P0.7 13 P1.0 12 P1.1 11 P1.2 ...
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... This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for custom features D2, E2 and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. C8051T630/1/2/3/4/5 Max Dimension Min 1. ...
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... C8051T630/1/2/3/4/5 Figure 4.2. QFN-20 Recommended PCB Land Pattern Table 4.2. QFN-20 PCB Land Pattern Dimesions Dimension Min C1 3.70 C2 3.70 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. ...
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... Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051T630/1/2/3/4/5 Conditions Min –55 – ...
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... C8051T630/1/2/3/4/5 5.2. Electrical Characteristics Table 5.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage (Note 1) Regulator in Normal Mode Regulator in Bypass Mode Digital Supply Current with V DD CPU Active Digital Supply Current with V DD CPU Inactive (not accessing ...
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... Port I/O push-pull –10 mA, Port I/O push-pull OH Output Low Voltage µ Input High Voltage Input Low Voltage Input Leakage Weak Pullup Off Current Weak Pullup On, V C8051T630/1/2/3/4/5 Conditions Min 0.1 DD — — — — 0 — — IN Rev. 1.0 ...
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... Parameter Input Voltage Range Bias Current Normal Mode Table 5.6. EPROM Electrical Characteristics Parameter EPROM Size C8051T630/1 EPROM Size C8051T632/3 EPROM Size C8051T634/5 Write Cycle Time (per Byte) Date Code 0935 and later 2 Programming Voltage ...
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... Use factory-calibrated settings Parameter Oscillator Frequency OSCLD = 11b Oscillator Supply Current 25 °C, V (from V ) OSCLCN Power Supply Variance Constant Temperature Temperature Variance Constant Supply C8051T630/1/2/3/4/5 Conditions Min Typ 24 24.5 = 3.0 V, — 450 DD — ±0.02 — ±20 Conditions Min ...
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... C8051T630/1/2/3/4/5 Table 5.9. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz sine-wave single-ended input below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion ...
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... Power Supply Rejection 1.2 V setting 2.4 V setting External Reference (REFBE = 0) Input Voltage Range Input Current Sample Rate = 500 ksps; VREF = 2.5 V Power Specifications Reference Bias Generator REFBE = 1, 2.4 V setting C8051T630/1/2/3/4/5 Conditions Min Typ — ±0.5 — 3.49 — ±40 — ...
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... C8051T630/1/2/3/4/5 Table 5.12. IDAC Electrical Characteristics V – +85 °C Full-scale output current set unless otherwise specified. DD Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Output Compliance Range Offset Error Full Scale Error 2 mA Full-Scale Output Current 25 °C Full Scale Error Tempco Power Supply ...
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... Inverting or Non-Inverting Input Voltage Range Input Offset Voltage Power Specifications Power Supply Rejection Powerup Time Supply Current at DC Mode 0 Mode 1 Mode 2 Mode 3 Note: Vcm is the common-mode voltage on CP0+ and CP0–. C8051T630/1/2/3/4/5 Conditions Min Typ — 240 — 240 — 400 — 400 — ...
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... C8051T630/1/2/3/4/5 5.3. Typical Performance Curves 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 5.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) 2.5 2.0 1.5 1.0 0.5 0 Figure 5.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = > SYSCLK (MHz) V > 1.8 V ...
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... The ADC is fully configurable under software control via Special Function Registers. The ADC may be con- figured to measure various different signals using the analog multiplexer described in Section “6.5. ADC0 Analog Multiplexer (C8051T630/2/4 only)” on page 43. The voltage reference for the ADC is selected as described in Section “9. Voltage Reference Options” on page 52. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1 ...
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... C8051T630/1/2/3/4/5 6.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit. Conversion codes are represented as 10-bit unsigned integers ...
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... Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1 Overflow (AD0CM[2:0]=000, 001, 010, 011) SAR Clocks AD0TM=1 SAR Clocks AD0TM=0 Figure 6.2. 10-Bit ADC Track and Conversion Example Timing C8051T630/1/2/3/4/5 A. ADC Timing for External Trigger Source 15 Track Convert *Conversion Ends at rising edge 12 N/C Track Convert *Conversion Ends at rising edge ...
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... C8051T630/1/2/3/4/5 6.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in delayed track- ing mode, three SAR clocks are used for tracking at the start of every conversion ...
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... Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0). 1 AD08BE 8-Bit Mode Enable. 0: ADC operates in 10-bit mode (normal). 1: ADC operates in 8-bit mode. Note: When AD08BE is set to 1, the AD0LJST bit is ignored. 0 AMP0GN0 ADC Gain Control Bit. 0: Gain = 0.5 1: Gain = 1 C8051T630/1/2/3/4 AD0LJST R Function – ...
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... C8051T630/1/2/3/4/5 SFR Definition 6.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10- bit ADC0 Data Word. For AD0LJST = 1: Bits 7– ...
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... ADC0 start-of-conversion source is write AD0BUSY. 001: ADC0 start-of-conversion source is overflow of Timer 0. 010: ADC0 start-of-conversion source is overflow of Timer 2. 011: ADC0 start-of-conversion source is overflow of Timer 1. 100: ADC0 start-of-conversion source is rising edge of external CNVSTR. 101: ADC0 start-of-conversion source is overflow of Timer 3. 11x: Reserved. C8051T630/1/2/3/4 AD0BUSY AD0WINT R/W R/W ...
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... C8051T630/1/2/3/4/5 6.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
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... ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC5 Bit Name 7:0 ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits. C8051T630/1/2/3/4 ADC0LTH[7:0] R Function ADC0LTL[7:0] R/W 0 ...
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... C8051T630/1/2/3/4/5 6.4.1. Window Detector Example Figure 6.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ...
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... ADC0 Analog Multiplexer (C8051T630/2/4 only) ADC0 on the C8051T630/2/4 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 0 and 1 I/O pins, the on-chip temperature sen- sor, or the positive power supply (V described in SFR Definition 6.9. ...
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... C8051T630/1/2/3/4/5 SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xBB Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input Selection. 00000: 00001: 00010: 00011: 00100: ...
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... Temperature Sensor (C8051T630/2/4 only) An on-chip temperature sensor is included on the C8051T630/2/4 which can be directly accessed via the ADC multiplexer. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured to connect to the temperature sensor. The temperature sensor transfer function is shown in Figure 7 ...
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... C8051T630/1/2/3/4/5 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 7.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius 46 0.00 20.00 40.00 Temperature (degrees C) Rev. 1.0 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 -2.00 -3 ...
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... The temperature sensor offset information is left-justified. One LSB of this measurement is equivalent to one LSB of the ADC output under the measurement conditions. 5:0 Unused Unused. Read = 000000b; Write = Don’t Care. C8051T630/1/2/3/4 TOFF[9:2] R/W Varies ...
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... C8051T630/1/2/3/4/5 8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only) The C8051T630/2/4 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maxi- mum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see SFR Defini- tion 8 ...
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... Figure 8.2. IDA0 Data Word Mapping The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default, the IDAC is set to a full-scale output current of 2 mA. The IDA0OMD bits can also be configured to provide full-scale output currents 0.5 mA, as shown in SFR Definition 8.1. C8051T630/1/2/3/4 ...
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... C8051T630/1/2/3/4/5 SFR Definition 8.1. IDA0CN: IDA0 Control Bit 7 6 IDA0EN IDA0CM[2:0] Name R/W Type 0 1 Reset SFR Address = 0xB9 Bit Name 7 IDA0EN IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. 6:4 IDA0CM[2:0] IDA0 Update Source Select bits. 000: DAC output updates on Timer 0 overflow. ...
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... Bit 7 6 IDA0[1:0] Name R/W Type 0 0 Reset SFR Address = 0x96 Bit Name 7:6 IDA0[1:0] IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit IDA0 Data Word. 5:0 Unused Unused. Read = 000000b. Write = Don’t care. C8051T630/1/2/3/4 IDA0[9:2] R Function Function Rev. 1.0 ...
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... BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in Table 5.11. The C8051T630/2/4 devices also include an on-chip voltage reference circuit which consists of a 1.2 V, temperature stable bandgap voltage reference generator and a selectable-gain output buffer amplifier. The buffer is configured for gain using the REFBGS bit in register REF0CN ...
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... Voltage Reference R1 Circuit VREF GND 0 + 4.7F 0.1F VDD 1 Recommended Bypass Capacitors Figure 9.1. Voltage Reference Functional Block Diagram Rev. 1.0 C8051T630/1/2/3/4/5 To ADC, IDAC, EN Internal Oscillators, Bias Generator Reference, TempSensor IOSCEN EN Temp Sensor To Analog Mux EN 1x/2x 1.2V Reference REFBE REFBGS ...
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... C8051T630/1/2/3/4/5 SFR Definition 9.1. REF0CN: Reference Control Bit 7 6 REFBGS Name R/W R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7 REFBGS Reference Buffer Gain Select. This bit selects between 1x and 2x gain for the on-chip voltage reference buffer Gain 1: 1x Gain 6:5 Unused Unused. Read = 00b ...
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... Voltage Regulator (REG0) C8051T630/1/2/3/4/5 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to DD help reduce current consumption in low-power applications. These modes are accessed through the REG0CN register (SFR Definition 10 ...
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... C8051T630/1/2/3/4/5 SFR Definition 10.1. REG0CN: Voltage Regulator Control Bit 7 6 STOPCF BYPASS Name R/W R/W Type 0 0 Reset SFR Address = 0xC7 Bit Name 7 STOPCF Stop Mode Configuration. This bit configures the regulator’s behavior when the device enters STOP mode. 0: Regulator is still active in STOP mode. Any enabled reset source will reset the device ...
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... Comparator0 C8051T630/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 11.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 asyn- chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is not active ...
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... C8051T630/1/2/3/4/5 The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini- tion 11.2). Selecting a longer response time reduces the Comparator supply current. CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- ...
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... CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. 1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051T630/1/2/3/4 CP0FIF CP0HYP[1:0] R/W R/W R/W 0 ...
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... C8051T630/1/2/3/4/5 SFR Definition 11.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. ...
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... Comparator Multiplexer C8051T630/1/2/3/4/5 devices include an analog input multiplexer to connect Port I/O pins to the compara- tor inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 11.3). The CMX0P3–CMX0P0 bits select the Comparator0 positive input; the CMX0N3–CMX0N0 bits select the Comparator0 negative input ...
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... C8051T630/1/2/3/4/5 SFR Definition 11.3. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[3:0] Name R/W Type 1 1 Reset SFR Address = 0x9F Bit Name 7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1xxx: 3:0 CMX0P[3:0] Comparator0 Positive Input MUX Selection. ...
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... ACCUMULATOR RESET CLOCK STOP IDLE Figure 12.1. CIP-51 Block Diagram C8051T630/1/2/3/4/5 Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security ...
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... C8051T630/1/2/3/4/5 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. Clocks to Execute 1 Number of Instructions 26 12.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ ...
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... direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte C8051T630/1/2/3/4/5 Bytes Rev. 1.0 Clock Cycles ...
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... C8051T630/1/2/3/4/5 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through Carry SWAP A Swap nibbles of A Data Transfer ...
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... Compare immediate to Register and jump if not equal CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation C8051T630/1/2/3/4/5 Bytes Rev. 1.0 Clock Cycles ...
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... C8051T630/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00– ...
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... The DPL register is the low byte of the 16-bit DPTR. SFR Definition 12.2. DPH: Data Pointer High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x83 Bit Name 7:0 DPH[7:0] Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. C8051T630/1/2/3/4 DPL[7:0] R Function DPH[7:0] R ...
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... C8051T630/1/2/3/4/5 SFR Definition 12.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incre- mented before every PUSH operation. The SP register defaults to 0x07 after reset. ...
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... The OV bit is cleared the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases User Flag 1. This is a bit-addressable, general purpose flag for use under software control. 0 PARITY Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. C8051T630/1/2/3/4 RS[1:0] R/W R Function Rev ...
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... The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory organization of the C8051T630/1/2/3/4/5 device family is shown in Figure 13.1 C8051T630/1 CODE MEMORY ...
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... Program Memory The CIP-51 core has program memory space. The C8051T630/1 implements 8192 bytes of this program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from addresses 0x0000 to 0x1FFF. Note that 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for fac- tory use and are not available for user program storage. The C8051T632/3 implements 4096 bytes of EPROM program memory space ...
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... C8051T630/1/2/3/4/5 13.2.1.1. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW ...
Page 75
... MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL determines which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. C8051T630/1/2/3/4 R/W R/W ...
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... SFRs used to configure and access the sub-systems unique to the C8051T630/1/2/3/4/5. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 14.1 lists the SFRs implemented in the C8051T630/1/2/3/4/5 device fam- ily. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF ...
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... Interrupt Priority IP 0xE4 INT0/INT1 Configuration IT01CF 0xB3 Internal Oscillator Calibration OSCICL 0xB2 Internal Oscillator Control OSCICN 0xE3 Low-Frequency Oscillator Control OSCLCN 0xB1 External Oscillator Control OSCXCN 0x80 Port 0 Latch P0 0xFE Port 0 Mask Configuration P0MASK C8051T630/1/2/3/4/5 Description Rev. 1.0 Page 170 102 ...
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... C8051T630/1/2/3/4/5 Table 14.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xFD Port 0 Match Configuration P0MAT 0xF1 Port 0 Input Mode Configuration P0MDIN 0xA4 Port 0 Output Mode Configuration P0MDOUT 0xD4 Port 0 Skip P0SKIP ...
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... Temperature Sensor Offset Measurement High TOFFH 0x85 Temperature Sensor Offset Measurement Low TOFFL 0xFF V VDM0CN DD 0xE1 Port I/O Crossbar Control 0 XBR0 0xE2 Port I/O Crossbar Control 1 XBR1 C8051T630/1/2/3/4/5 Description Monitor Control Rev. 1.0 Page 137 133 135 139 70 163 165 164 165 175 ...
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... C8051T630/1/2/3/4/5 15. Interrupts The C8051T630/1/2/3/4/5 includes an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associ- ated interrupt-pending flag(s) located in an SFR ...
Page 81
... MCU Interrupt Sources and Vectors The C8051T630/1/2/3/4/5 MCUs support 14 interrupt sources. Software can simulate an interrupt by set- ting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 15 ...
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... C8051T630/1/2/3/4/5 Table 15.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B Port Match 0x0043 ADC0 Window Com- 0x004B ...
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... This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. 0 EX0 Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 input. C8051T630/1/2/3/4 ET2 ES0 ET1 R/W R/W ...
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... C8051T630/1/2/3/4/5 SFR Definition 15.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Unused. Read = 1, Write = Don't Care. 6 PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. ...
Page 85
... This bit sets the masking of the Port Match Event interrupt. 0: Disable all Port Match interrupts. 1: Enable interrupt requests generated by a Port Match. 0 ESMB0 Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051T630/1/2/3/4 ECP0 EPCA0 EADC0 EWADC0 R/W ...
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... C8051T630/1/2/3/4/5 SFR Definition 15.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 Reserved Name R/W R/W Type 0 0 Reset SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. ...
Page 87
... IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. C8051T630/1/2/3/4/5 IT1 IN1PL /INT1 Interrupt ...
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... C8051T630/1/2/3/4/5 SFR Definition 15.5. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: /INT1 input is active low. 1: /INT1 input is active high. 6:4 IN1SL[2:0] INT1 Port Pin Selection Bits. These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar ...
Page 89
... Refer to the “C2 Interface Specification” available at http://www.silabs.com for details on com- municating via the C2 interface. Section “26. C2 Interface” on page 210 has information about C2 register addresses for the C8051T630/1/2/3/4/5. 16.1.1. EPROM Write Procedure 1. Reset the device using the RST pin. ...
Page 90
... Reset the device: Write 0x02 and then 0x00 to the DEVCTL register. 16.2. Security Options The C8051T630/1/2/3/4/5 devices provide security options to prevent unauthorized viewing of proprietary program code and constants. A security byte in EPROM address space can be used to lock the program memory from being read or written across the C2 interface. When read, the RDLOCK and WRLOCK bits in register EPSTAT will indicate the lock status of the location currently addressed by EPADDR. Table 16.1 shows the security byte decoding. See Section “ ...
Page 91
... The EPBusy bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete. The 16-bit results will be available in the CRC1-0 registers. CRC1 is the MSB, and CRC0 is the LSB. The polynomial for the 16-bit CRC calculation is 0x1021 C8051T630/1/2/3/4/5 Rev. 1.0 91 ...
Page 92
... SFR Definition 17.1 describes the Power Control Register (PCON) used to control the C8051T630/1/2/3/4/5's stop and idle power man- agement modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 19 ...
Page 93
... SUSPEND bit. If the wake event (port match or Timer 3 overflow) was configured to generate an inter- rupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. C8051T630/1/2/3/4/5 Rev. 1.0 93 ...
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... C8051T630/1/2/3/4/5 SFR Definition 17.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 STOP Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. ...
Page 95
... Comparator 0 Px Px.x Low Frequency Oscillator Internal System Oscillator Clock External Oscillator EXTCLK Clock Select Drive Figure 18.1. Reset Sources C8051T630/1/2/3/4/5 VDD Supply Monitor + - Enable C0RSEF Missing Clock Detector (one- PCA shot) (Software Reset) WDT EN SWRSF EN ...
Page 96
... C8051T630/1/2/3/4/5 18.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V RST increases (V ramp time is defined as how fast V DD power-on and V monitor event timing ...
Page 97
... DD See Figure 18.2 for V monitor timing; note that the power-on-reset delay is not incurred after monitor reset. See Table 5.4 for complete electrical characteristics of the V C8051T630/1/2/3/4/5 Monitor to drop below V DD monitor is disabled by code and a software reset is performed, the monitor as a reset source before it is enabled and stabi- ...
Page 98
... C8051T630/1/2/3/4/5 SFR Definition 18.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT Name R/W R Type Varies Varies Reset SFR Address = 0xFF Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem resets until it is also selected as a reset source in register RSTSRC (SFR Def- inition 18.2). Selecting the V may generate a system reset ...
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... The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaf- fected by this reset. 18.8. Software Reset Software may force a reset by writing the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol- lowing a software forced reset. The state of the RST pin is unaffected by this reset. C8051T630/1/2/3/4/5 Rev. 1.0 99 ...
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... C8051T630/1/2/3/4/5 SFR Definition 18.2. RSTSRC: Reset Source Bit 7 6 MEMERR C0RSEF Name R R Type 0 Varies Reset SFR Address = 0xEF Bit Name Description 7 Unused Unused. 6 MEMERR EPROM Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable and Flag. 4 SWRSF Software Reset Force and Flag. ...
Page 101
... Oscillators and Clock Selection C8051T630/1/2/3/4/5 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscilla- tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 19.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the OSCLCN register ...
Page 102
... C8051T630/1/2/3/4/5 SFR Definition 19.1. CLKSEL: Clock Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA9 Bit Name 7:2 Unused Unused. Read = 000000b; Write = Don’t Care 1:0 CLKSL[1:0] System Clock Source Select Bits. 00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in register OSCICN ...
Page 103
... The internal oscillator period caPara1n be adjusted via the OSCICL register as defined by SFR Definition 19.2. On C8051T630/1/2/3/4/5 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency. The system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN ...
Page 104
... C8051T630/1/2/3/4/5 SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. 1: Internal H-F Oscillator Enabled. 6 IFRDY Internal H-F Oscillator Frequency Ready Flag. ...
Page 105
... Programmable Internal Low-Frequency (L-F) Oscillator All C8051T630/1/2/3/4/5 devices include a programmable low-frequency internal oscillator, which is cali- brated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock using the OSCLD bits in the OSCLCN register (see SFR Defi- nition 19.4). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’ ...
Page 106
... C8051T630/1/2/3/4/5 19.4. External Oscillator Drive Circuit The external oscillator circuit may drive an external capacitor or RC network. A CMOS clock may also pro- vide a clock input. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the EXTCLK pin as shown in Figure 19.1. The type of external oscillator must be selected in the OSCXCN reg- ister, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 19 ...
Page 107
... MHz 110 1.6 MHz f 3.2 MHz 111 C8051T630/1/2/3/4 R Function C Mode K Factor = 0 ...
Page 108
... C8051T630/1/2/3/4/5 19.4.1. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 19.1, “RC Mode”. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation, according to Equation 19 ...
Page 109
... SYSCLK 4 PCA 2 Lowest T0, T1 Priority 8 P0 (P0.0-P0. (P1.0-P1. (P2.0) Figure 20.1. Port I/O Functional Block Diagram C8051T630/1/2/3/4/5 Port Match XBR0, XBR1, P0MASK, P0MAT PnSKIP Registers P1MASK, P1MAT External Interrupts Priority EX0 and EX1 Decoder PnMDOUT, PnMDIN Registers P0 Digital I/O Crossbar 8 Cells ...
Page 110
... C8051T630/1/2/3/4/5 20.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 20.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1) ...
Page 111
... Port pin when the supply voltage is between (VDD + 0.6 V) and (VDD + 1.0 V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin is mini- mal. C8051T630/1/2/3/4/5 VDD VDD (WEAK) GND Rev ...
Page 112
... C8051T630/1/2/3/4/5 20.2. Assigning Port I/O Pins to Analog and Digital Functions Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digital or exter- nal interrupt functions should be configured for digital I/O. ...
Page 113
... Table 20.3. Port I/O Assignment for External Digital Event Capture Functions Digital Function External Interrupt 0 External Interrupt 1 Port Match C8051T630/1/2/3/4/5 Potentially Assignable Port Pins P0.0–P0.7 P0.0–P0.7 P0.0–P1.7 Rev. 1.0 SFR(s) used for ...
Page 114
... C8051T630/1/2/3/4/5 20.3. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 20.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5 Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource ...
Page 115
... RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. C8051T630/1/2/3/4/5 P0 CNVSTR 4 5 ...
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... C8051T630/1/2/3/4/5 20.4. Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT) ...
Page 117
... SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either GPIO pins. 0 URT0E UART I/O Output Enable. 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. C8051T630/1/2/3/4 CP0E SYSCKE SMB0E R/W ...
Page 118
... C8051T630/1/2/3/4/5 SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode) ...
Page 119
... Reset SFR Address = 0xFD Bit Name 7:0 P0MAT[7:0] Port 0 Match Value. Match comparison value used on Port 0 for bits in P0MASK which are set P0.n pin logic value is compared with logic LOW. 1: P0.n pin logic value is compared with logic HIGH. C8051T630/1/2/3/4 P0MASK[7:0] R Function ...
Page 120
... C8051T630/1/2/3/4/5 SFR Definition 20.5. P1MASK: Port 1 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xEE Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to the corresponding bits in P1MAT. 0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event. ...
Page 121
... Reset SFR Address = 0x80; Bit-Addressable Bit Name Description 7:0 P0[7:0] Port 0 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells con- figured for digital I/O. C8051T630/1/2/3/4 P0[7:0] R Write 0: Set output latch to logic LOW. 1: Set output latch to logic HIGH ...
Page 122
... C8051T630/1/2/3/4/5 SFR Definition 20.8. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled ...
Page 123
... Bit 7 6 Name Type 1 1 Reset SFR Address = 0x90; Bit-Addressable Bit Name Description 7:0 P1[7:0] Port 1 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells con- figured for digital I/O. C8051T630/1/2/3/4 P0SKIP[7:0] R Function P1[7:0] R Write 0: Set output latch to logic LOW ...
Page 124
... C8051T630/1/2/3/4/5 SFR Definition 20.12. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF2 Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled ...
Page 125
... R R Type 0 0 Reset SFR Address = 0xA0; Bit-Addressable Bit Name Description 7:1 Unused Unused. 0 P2[0] Port 2 Data. Sets the Port latch logic value or reads the Port pin logic state in Port cells con- figured for digital I/O. C8051T630/1/2/3/4 P1SKIP[6:0] R Function Write Don’t Care 0: Set output latch to logic LOW ...
Page 126
... C8051T630/1/2/3/4/5 SFR Definition 20.16. P2MDOUT: Port 2 Output Mode Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA6 Bit Name 7:1 Unused Unused. Read = 000000b; Write = Don’t Care 0 P2MDOUT[0] Output Configuration Bits for P2.0. 0: P2.0 Output is open-drain. 1: P2.0 Output is push-pull. ...
Page 127
... Hardware Slave Address Recognition Hardware ACK Generation IRQ Generation SMB0ADR SMB0ADM Figure 21.1. SMBus Block Diagram C8051T630/1/2/3/4 serial bus. Reads and writes Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL N Control Data Path SDA Control Control SMB0DAT FILTER Rev. 1.0 SCL ...
Page 128
... C8051T630/1/2/3/4/5 21.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum. ...
Page 129
... Devices that have detected the timeout condition must reset the communi- cation no later than 10 ms after detecting the timeout condition. C8051T630/1/2/3/4/5 R/W D7 ...
Page 130
... C8051T630/1/2/3/4/5 When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout ...
Page 131
... Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable C8051T630/1/2/3/4/5 SMBCS0 SMBus Clock Source ...
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... C8051T630/1/2/3/4/5 after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min- imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz ...
Page 133
... SMBCS[1:0] SMBus Clock Source Selection. These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 21.1. 00: Timer 0 Overflow 01: Timer 1 Overflow 10: Timer 2 High Byte Overflow 11: Timer 2 Low Byte Overflow C8051T630/1/2/3/4 EXTHOLD SMBTOE SMBFTE R ...
Page 134
... C8051T630/1/2/3/4/5 21.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 21.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER indicates whether a device is the master or slave during the current transfer ...
Page 135
... ARBLOST SMBus Arbitration Lost Indicator. 1 ACK SMBus Acknowledge SMBus Interrupt Flag. This bit is set by hardware under the conditions listed in Table 15.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. C8051T630/1/2/3/4 STA STO ACKRQ ARBLOST R/W R Read 0: SMBus operating in slave mode ...
Page 136
... C8051T630/1/2/3/4/5 Table 21.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: A START is generated. MASTER START is generated. SMB0DAT is written before the start of an TXMODE SMBus frame. A START followed by an address byte is STA received. A STOP is detected while addressed as a slave ...
Page 137
... GC General Call Address Enable. When hardware address recognition is enabled (EHACK = 1), this bit will deter- mine whether the General Call Address (0x00) is also recognized by hardware. 0: General Call Address is ignored. 1: General Call Address is recognized. C8051T630/1/2/3/4/5 GC bit Slave Addresses Recognized by Hardware 0 0x34 1 0x34, 0x00 (General Call) ...
Page 138
... C8051T630/1/2/3/4/5 SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask Bit 7 6 Name Type 1 1 Reset SFR Address = 0xE7 Bit Name 7:1 SLVM[6:0] SMBus Slave Address Mask. Defines which bits of register SMB0ADR are compared with an incoming address byte, and which bits are ignored. Any bit set SLVM[6:0] enables compari- sons with the corresponding bit in SLV[6:0] ...
Page 139
... The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. C8051T630/1/2/3/4 ...
Page 140
... C8051T630/1/2/3/4/5 21.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP ...
Page 141
... ACK when hardware ACK generation is enabled. Interrupts with Hardware ACK Enabled (EHACK = 1) S SLA R Interrupts with Hardware ACK Disabled (EHACK = 0) Received by SMBus Interface Transmitted by SMBus Interface Figure 21.6. Typical Master Read Sequence C8051T630/1/2/3/4/5 A Data Byte A Data Byte S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Rev ...
Page 142
... C8051T630/1/2/3/4/5 21.5.3. Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc- tion bit (WRITE in this case) is received ...
Page 143
... SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ- ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi- cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification. C8051T630/1/2/3/4/5 Interrupts with Hardware ACK Enabled (EHACK = 1) A ...
Page 144
... C8051T630/1/2/3/4/5 Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 A master data or address byte was transmitted; ACK received. A master data byte was ...
Page 145
... START. Lost arbitration due to a 0001 detected STOP. Lost arbitration while transmit- 0000 ting a data byte as master. C8051T630/1/2/3/4/5 Typical Response Options No action required (expecting STOP condition). Load SMB0DAT with next data byte to transmit. No action required (expecting Master to end transfer). Clear STO. ...
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... C8051T630/1/2/3/4/5 Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK received. 1100 A master data or address byte was transmitted; ACK received. A master data byte was ...
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... START. Lost arbitration due to a 0001 detected STOP. Lost arbitration while transmit- 0000 ting a data byte as master. C8051T630/1/2/3/4/5 Typical Response Options No action required (expecting STOP condition). Load SMB0DAT with next data byte to transmit. No action required (expecting Master to end transfer). Clear STO. ...
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... C8051T630/1/2/3/4/5 22. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “22.1. Enhanced Baud Rate Generation” on page 149). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte ...
Page 149
... Timer 1 clock frequency is selected as described in Section “24. Timers” on page 169. A quick ref- erence for typical baud rates and system clock frequencies is given in Table 22.1 through Table 22.2. The internal oscillator may still generate the system clock when the external oscillator is driving Timer 1. C8051T630/1/2/3/4/5 UART Overflow ...
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... C8051T630/1/2/3/4/5 22.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 22.3. Figure 22.3. UART Interconnect Diagram 22.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit ...
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... SBUF0 and RB80 will not be loaded and the RI0 flag will not be set UART0 interrupt will occur if enabled when either TI0 or RI0 is set to 1. MARK START D0 D1 BIT SPACE BIT TIMES BIT SAMPLING Figure 22.5. 9-Bit UART Timing Diagram C8051T630/1/2/3/4 Rev. 1.0 STOP D7 D8 BIT ...
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... C8051T630/1/2/3/4/5 22.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1 ...
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... Set hardware when a byte of data has been received by UART0 (set at the STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1 causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. C8051T630/1/2/3/4 REN0 ...
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... C8051T630/1/2/3/4/5 SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x99 Bit Name 7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB). This SFR accesses two registers; a transmit shift register and a receive latch register. ...
Page 155
... Notes: – 1. SCA1 SCA0 and T1M bit definitions can be found Don’t care. C8051T630/1/2/3/4/5 Frequency: 24.5 MHz Oscillator Timer Clock SCA1–SCA0 Divide Source (pre-scale Factor select) 106 SYSCLK XX 212 SYSCLK ...
Page 156
... C8051T630/1/2/3/4/5 23. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers ...
Page 157
... NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section “20. Port Input/Output” on page 109 for general purpose port I/O and crossbar information. C8051T630/1/2/3/4/5 Rev. 1.0 157 ...
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... C8051T630/1/2/3/4/5 23.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins ...
Page 159
... NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig- nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 23.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. C8051T630/1/2/3/4/5 Slave Device MISO ...
Page 160
... C8051T630/1/2/3/4/5 3-wire slave mode is active when NSSMD1 (SPI0CN. and NSSMD0 (SPI0CN. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus ...
Page 161
... Figure 23.5. Master Mode Data/Clock Timing SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 MISO MSB Bit 6 NSS (4-Wire Mode) Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0) C8051T630/1/2/3/4/5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 Rev. 1.0 Bit 2 ...
Page 162
... C8051T630/1/2/3/4/5 SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) 23.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register ...
Page 163
... RXBMT = 1 when in Master Mode. Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 23.1 for timing parameters. C8051T630/1/2/3/4 ...
Page 164
... C8051T630/1/2/3/4/5 SFR Definition 23.2. SPI0CN: SPI0 Control Bit 7 6 SPIF WCOL Name R/W R/W Type 0 0 Reset SFR Address = 0xF8; Bit-Addressable Bit Name 7 SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software ...
Page 165
... SPI0DAT[7:0] SPI0 Transmit and Receive Data. The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode. A read of SPI0DAT returns the contents of the receive buffer. C8051T630/1/2/3/4 SCR[7:0] ...
Page 166
... C8051T630/1/2/3/4/5 SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.9. SPI Master Timing (CKPHA = 1) ...
Page 167
... Figure 23.10. SPI Slave Timing (CKPHA = 0) NSS CKL SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 23.11. SPI Slave Timing (CKPHA = 1) C8051T630/1/2/3/4/5 CKL T T SIS SIH T SOH T SIH Rev. 1 SDZ ...
Page 168
... C8051T630/1/2/3/4/5 Table 23.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing (See Figure 23.8 and Figure 23.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge to MISO Change MIH Slave Mode Timing (See Figure 23.10 and Figure 23.11) ...
Page 169
... The input signal need not be peri- odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. C8051T630/1/2/3/4/5 Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload Rev ...
Page 170
... C8051T630/1/2/3/4/5 SFR Definition 24.1. CKCON: Clock Control Bit 7 6 T3MH T3ML Name R/W R/W Type 0 0 Reset SFR Address = 0x8E Bit Name 7 T3MH Timer 3 High Byte Clock Select. Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only). ...
Page 171
... TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal INT0 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see SFR Definition 15.5). C8051T630/1/2/3/4/5 GATE0 INT0 Counter/Timer ...
Page 172
... C8051T630/1/2/3/4/5 Pre-scaled Clock SYSCLK T0 GATE0 Crossbar IN0PL XOR /INT0 Figure 24.1. T0 Mode 0 Block Diagram 24.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun- ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. ...
Page 173
... INT0 is active as defined by bit IN0PL in register IT01CF (see Section “15.3. INT0 and INT1 External Interrupts” on page 87 for details on the external input signals INT0 and INT1). T0M Pre-scaled Clock SYSCLK T0 Crossbar GATE0 IN0PL XOR /INT0 Figure 24.2. T0 Mode 2 Block Diagram C8051T630/1/2/3/4/5 TMOD IT01CF ...
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... C8051T630/1/2/3/4/5 24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 175
... IT0 Interrupt 0 Type Select. This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 15.5). 0: INT0 is level triggered. 1: INT0 is edge triggered. C8051T630/1/2/3/4 TF0 TR0 IE1 R/W ...
Page 176
... C8051T630/1/2/3/4/5 SFR Definition 24.3. TMOD: Timer Mode Bit 7 6 GATE1 C/T1 Name R/W R/W Type 0 0 Reset SFR Address = 0x89 Bit Name 7 GATE1 Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in register IT01CF (see SFR Definition 15 ...
Page 177
... The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 24.5. TL1: Timer 1 Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8B Bit Name 7:0 TL1[7:0] Timer 1 Low Byte. The TL1 register is the low byte of the 16-bit Timer 1. C8051T630/1/2/3/4 TL0[7:0] R Function TL1[7:0] R ...
Page 178
... C8051T630/1/2/3/4/5 SFR Definition 24.6. TH0: Timer 0 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. SFR Definition 24.7. TH1: Timer 1 High Byte Bit ...
Page 179
... CKCON T2XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 24.4. Timer 2 16-Bit Mode Block Diagram C8051T630/1/2/3/4/5 To SMBus TL2 Overflow TCLK TR2 TMR2L TMR2H TMR2RLL TMR2RLH Reload Rev. 1.0 To ADC, SMBus TF2H Interrupt TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK 179 ...
Page 180
... C8051T630/1/2/3/4/5 24.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 24.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode ...
Page 181
... LFO to achieve an accurate reading. CKCON T2XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Low-Frequency Oscillator Figure 24.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram C8051T630/1/2/3/4 TCLK TR2 TMR2L TMR2H Capture TF2CEN TMR2RLL TMR2RLH Rev. 1.0 TF2H Interrupt TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK 181 ...
Page 182
... C8051T630/1/2/3/4/5 SFR Definition 24.8. TMR2CN: Timer 2 Control Bit 7 6 TF2H TF2L TF2LEN Name R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name 7 TF2H Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000 ...
Page 183
... Name Type 0 0 Reset SFR Address = 0xCC Bit Name 7:0 TMR2L[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer bit mode, TMR2L contains the 8-bit low byte timer value. C8051T630/1/2/3/4 TMR2RLL[7:0] R Function TMR2RLH[7:0] ...
Page 184
... C8051T630/1/2/3/4/5 SFR Definition 24.12. TMR2H Timer 2 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer bit mode, TMR2H contains the 8-bit high byte timer value. ...
Page 185
... TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from 0xFF to 0x00. CKCON T3XCLK[1: SYSCLK / 12 00 External Clock / TR3 Internal LFO / SYSCLK Figure 24.7. Timer 3 16-Bit Mode Block Diagram C8051T630/1/2/3/4 TCLK TMR3L TMR3H TMR3RLL TMR3RLH Reload Rev. 1.0 To ADC TF3H Interrupt TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK1 T3XCLK0 ...
Page 186
... C8051T630/1/2/3/4/5 24.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 24.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode ...
Page 187
... LFO to achieve an accurate reading. This means that the LFO/8 should not be selected as the timer clock source in this mode. CKCON T3XCLK[1: SYSCLK / External Clock / 8 01 SYSCLK 1 Low-Frequency Oscillator Figure 24.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram C8051T630/1/2/3/4 TCLK TR3 TMR3L TMR3H Capture TF3CEN TMR3RLL TMR3RLH Rev. 1.0 TF3H Interrupt TF3L ...
Page 188
... C8051T630/1/2/3/4/5 SFR Definition 24.13. TMR3CN: Timer 3 Control Bit 7 6 TF3H TF3L TF3LEN Name R/W R/W Type 0 0 Reset SFR Address = 0x91 Bit Name 7 TF3H Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000 ...
Page 189
... Name Type 0 0 Reset SFR Address = 0x94 Bit Name 7:0 TMR3L[7:0] Timer 3 Low Byte. In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8-bit mode, TMR3L contains the 8-bit low byte timer value. C8051T630/1/2/3/4 TMR3RLL[7:0] R Function TMR3RLH[7:0] ...
Page 190
... C8051T630/1/2/3/4/5 SFR Definition 24.17. TMR3H Timer 3 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x95 Bit Name 7:0 TMR3H[7:0] Timer 3 High Byte. In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In 8-bit mode, TMR3H contains the 8-bit high byte timer value. ...
Page 191
... Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled. See Section 25.4 for details. Capture/Compare Figure 25.1. PCA Block Diagram C8051T630/1/2/3/4/5 SYSCLK/12 SYSCLK/4 Timer 0 Overflow PCA ...
Page 192
... C8051T630/1/2/3/4/5 25.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. ...
Page 193
... PCA0CPMn PCA0CN PCA Counter/Timer 11-bit Overflow PCA Counter/Timer 16- bit Overflow ECCF0 PCA Module 0 (CCF0) ECCF1 PCA Module 1 (CCF1) ECCF2 PCA Module 2 (CCF2) Figure 25.3. PCA Interrupt Block Diagram C8051T630/1/2/3/4/5 PCA0MD PCA0PWM Set bit Operation Rev. 1.0 EPCA0 EA Interrupt 0 0 Priority 1 1 ...
Page 194
... C8051T630/1/2/3/4/5 25.3. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high-speed output, frequency output 11-bit pulse width modulator, or 16-bit pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP- 51 system controller ...
Page 195
... Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall- ing-edge caused the capture. CEXn Port I/O Crossbar Figure 25.4. PCA Capture Mode Diagram Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. C8051T630/1/2/3/4/5 PCA Interrupt PCA0CPMn PCA0CN ...
Page 196
... C8051T630/1/2/3/4/5 25.3.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled ...
Page 197
... ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1. Write to PCA0CPLn 0 ENB Reset PCA0CPMn Write PCA0CPHn ENB PCA0CPLn Enable 16-bit Comparator PCA PCA0L Timebase Figure 25.6. PCA High-Speed Output Mode Diagram C8051T630/1/2/3/4 PCA0CPHn Match 1 TOGn Toggle PCA0H Rev. 1.0 PCA Interrupt PCA0CN ...
Page 198
... C8051T630/1/2/3/4/5 25.3.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of the square wave is then defined by Equation 25.1. ...
Page 199
... ENB Reset Write to PCA0CPHn ENB 1 PCA0PWM PCA0CPMn Figure 25.8. PCA 8-Bit PWM Mode Diagram C8051T630/1/2/3/4/5 256 PCA0CPHn – -------------------------------------------------- - = 256 PCA0CPHn COVF PCA0CPLn 8-bit match Enable S Comparator R PCA Timebase PCA0L Overflow Rev. 1.0 CEXn SET Q Crossbar Port I/O Q CLR 199 ...
Page 200
... C8051T630/1/2/3/4/5 25.3.5.2. 9/10/11-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto- Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data written to define the duty cycle should be right-justified in the registers. The auto-reload registers are accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1 ...