F272-BAG-T STMicroelectronics, F272-BAG-T Datasheet - Page 85
F272-BAG-T
Manufacturer Part Number
F272-BAG-T
Description
MCU 16BIT 256K FLASH 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.F272-BAGE-T-TR.pdf
(182 pages)
Specifications of F272-BAG-T
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-TQFP, 144-VQFP
Processor Series
ST10F27x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
ASC, CAN, I2C, SSC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
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Part Number
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Quantity
Price
Company:
Part Number:
F272-BAG-T
Manufacturer:
STMicroelectronics
Quantity:
10 000
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Part Number:
F272-BAG-T-TR
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ST10F272B/ST10F272E
Figure 18. Asynchronous power-on RESET (EA = 0)
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the
application. It may be triggered by the hardware of the application. Internal hardware logic
and application circuitry are described in Reset circuitry chapter and Figures 30,
It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
Note 1. 3 to 8 TCL depending on clock source selection.
V
V
XTAL1
RPD
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
ALE
RST
DD
18
≥ 1.2 ms (for resonator oscillation + PLL stabilization)
≥ 10.2 ms (for crystal oscillation + PLL stabilization)
≥ 1 ms (for on-chip VREG stabilization)
not transparent
...
transparent
transparent
system start-up configuration
≥ 50 ns
≤ 500 ns
Latching point of Port0 for
3..4 TCL
3..8 TCL
1)
not t.
not t.
not t.
8 TCL
System reset
31
and 32.
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