ST7FMC2S6T3 STMicroelectronics, ST7FMC2S6T3 Datasheet - Page 42
ST7FMC2S6T3
Manufacturer Part Number
ST7FMC2S6T3
Description
IC MCU 8BIT 32K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FMC2S4T6.pdf
(309 pages)
Specifications of ST7FMC2S6T3
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-LQFP
Processor Series
ST7FMC2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
60
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FMC2S6T3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the Wait
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the Halt modes (see column “Exit from
Halt” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting Halt
mode, the first one serviced can only be an inter-
rupt with exit from Halt mode capability and it is se-
lected through the same decision process shown
in
Note: If an interrupt, that is not able to Exit from
Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced
after the first one serviced.
Figure 22. Concurrent Interrupt Management
Figure 23. Nested Interrupt Management
42/309
1
Figure
21.
11 / 10
11 / 10
MAIN
MAIN
RIM
RIM
IT2
IT2
IT1
IT1
IT4
MCES
MCES
IT1
IT4
IT0
IT0
7.4 CONCURRENT & NESTED MANAGEMENT
The following
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, MCES. The software priority
is given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
IT3
IT3
IT1
23. The interrupt hardware priority is given
IT4
IT2
Figure 22
10
10
SOFTWARE
PRIORITY
LEVEL
SOFTWARE
PRIORITY
LEVEL
MAIN
MAIN
and
3
3
3
3
3
3
3/0
3
3
2
1
3
3
3/0
Figure 23
I1
I1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 0
0 1
1 1
1 1
show two
I0
I0
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