Z8F012ASB020SG Zilog, Z8F012ASB020SG Datasheet - Page 182
Z8F012ASB020SG
Manufacturer Part Number
Z8F012ASB020SG
Description
IC ENCORE XP MCU FLASH 1K 8SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F011ASB020EG.pdf
(282 pages)
Specifications of Z8F012ASB020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Eeprom Size
16 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
Z8F012Ax
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4039
Z8F012ASB020SG
Z8F012ASB020SG
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PS022825-0908
Power Failure Protection
Optimizing NVDS Memory Usage for Execution Speed
read operations to illegal addresses. Also, the user code must pop the address byte off the
stack.
The read routine uses 9 bytes of stack space in addition to the one byte of address pushed
by the user. Sufficient memory must be available for this stack usage.
Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution
time. A read operation takes between 44 μs and 489 μs (assuming a 20 MHz system
clock). Slower system clock speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff. Illegal read operations have a 2 μs execution time.
The status byte returned by the NVDS read routine is zero for successful read, as
determined by a CRC check. If the status byte is non-zero, there was a corrupted value in
the NVDS array at the location being read. In this case, the value returned in R0 is the byte
most recently written to the array that does not have a CRC error.
The NVDS routines employ error checking mechanisms to ensure a power failure
endangers only the most recently written byte. Bytes previously written to the array are
not perturbed.
A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
The NVDS read time varies drastically, this discrepancy being a trade-off for minimizing
the frequency of writes that require post-write page erases (see
read time of address N is a function of the number of writes to addresses other than N
since the most recent write to address N, as well as the number of writes since the most
recent page erase. Neglecting effects caused by page erases and results caused by the ini-
tial condition in which the NVDS is blank, a rule of thumb is that every write since the
most recent page erase causes read times of unwritten addresses to increase by 1 μs, up to
a maximum of (511-NVDS_SIZE) μs.
Table 104. NVDS Read Time
Operation
Read (16 byte array)
Read (64 byte array)
Minimum
Latency
875
876
Maximum
Latency
9961
8952
Z8 Encore! XP
Table
Product Specification
Non-Volatile Data Storage
104). The NVDS
®
F082A Series
171
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