Z8F011ASB020SG Zilog, Z8F011ASB020SG Datasheet - Page 134
Z8F011ASB020SG
Manufacturer Part Number
Z8F011ASB020SG
Description
IC ENCORE XP MCU FLASH 1K 8SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F011ASB020EG.pdf
(282 pages)
Specifications of Z8F011ASB020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Eeprom Size
16 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
Z8F011Ax
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
8
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4011
Z8F011ASB020SG
Z8F011ASB020SG
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PS022825-0908
Hardware Overflow
Automatic Powerdown
Single-Shot Conversion
can output values across the entire 11-bit range, from -1024 to +1023. In
SINGLE-ENDED mode, the output generally ranges from 0 to +1023, but offset errors
can cause small negative values.
The ADC registers actually return 13 bits of data, but the two LSBs are intended for com-
pensation use only. When the software compensation routine is performed on the 13 bit
raw ADC value, two bits of resolution are lost because of a rounding error. As a result, the
final value is an 11-bit number.
When the hardware overflow bit (OVF) is set in ADC Data Low Byte (ADCD_L) register,
all other data bits are invalid. The hardware overflow bit is set for values greater than V
and less than -V
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered down. From this powerdown state, the
ADC requires 40 system clock cycles to power up. The ADC powers up when a
conversion is requested by the ADC Control register.
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Follow the steps below for setting up the ADC and initiating a single-
shot conversion:
1. Enable the desired analog inputs by configuring the general-purpose I/O pins for
2. Write the
3. Write to the
alternate analog function. This configuration disables the digital input and output
drivers.
The bit fields in the ADC Control register can be written simultaneously (the ADC
can be configured and enabled with the same write instruction):
–
–
–
–
Write to
mode, as well as unbuffered or buffered mode.
Write the
voltage reference level or to disable the internal reference. The
is. contained in the
Write to the
sources (different input pins available depending on the device).
Clear CONT to 0 to select a single-shot conversion.
ADC Control/Status Register 1
ref
ADC Control Register 0
(DIFFERENTIAL mode).
BUFMODE[2:0]
REFSELH
ANAIN[3:0]
ADC Control Register
bit of the pair {
to select SINGLE-ENDED or DIFFERENTIAL
field to select from the available analog input
to configure the ADC and begin the conversion.
to configure the ADC.
REFSELH
0.
Z8 Encore! XP
,
REFSELL
Product Specification
Analog-to-Digital Converter
} to select the internal
®
F082A Series
REFSELL
bit
ref
123
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