LPC3154FET208,551 NXP Semiconductors, LPC3154FET208,551 Datasheet - Page 40

• Manufacturer Part Number: LPC3154FET208,551
• Description: IC ARM9 MCU USB OTG 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3154FET208,551

• Package / Case: 208-TFBGA
• Voltage - Supply (vcc/vdd): 1.1 V ~ 1.3 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 180MHz
• Number Of I /o: 10
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Ram Size: 192K x 8
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, I2S, SPI, UART
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935287563551

NXP Semiconductors
LPC3152_3154
Preliminary data sheet
Fig 10. Audio paths block diagram
I2SRX_DATA0
I2STX_DATA0
I2SRX_BCK0
I2STX_BCK0
I2STX_CLK0
I2SRX_WS0
I2STX_WS0
ADC_VINL
ADC_VINR
ADC_TINR
ADC_TINL
ADC_MIC
6.32.1 I
ANALOG DIE/AUDIO CODEC
LPC3152/3154
MUX_L0
MUX_R0
The I
I
Remark: In the LPC3152/3154, the I
internally connected to the analog die.
2
2
•
•
S standard.
S0/1 digital audio input/output
Audio codec on the analog die (see
– Class AB amplifier
– Stereo Analog-to-Digital Converter (SADC)
– analog inputs/outputs
– Analog Volume Control (AVC)
– Stereo Digital-to-Analog Converter (SDAC)
I
2
2
S and I
S0/1 audio module provides a 3-wire digital audio interface that complies with the
I
2
MUX_R1
MUX_L1
S0
2
C interfaces on the analog die for communication with the digital die.
STEREO ADC
All information provided in this document is subject to legal disclaimers.
SADC
Rev. 0.12 — 27 May 2010
APB
I2SRX_1
signals
I
2
I
2
S1
S
2
S0 interface is pinned out. The I
AVC
Section
I2STX_1
signals
DMUX
7.2):
I
I
2
2
C1
SDAC
LPC3152/3154
SDAC
C
CLASS
002aae558
2
S1 interface is
AB
© NXP B.V. 2010. All rights reserved.
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HP_FCR
HP_OUTR
HP_OUTC
HP_OUTL
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