LPC3154FET208,551 NXP Semiconductors, LPC3154FET208,551 Datasheet - Page 27

• Manufacturer Part Number: LPC3154FET208,551
• Description: IC ARM9 MCU USB OTG 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3154FET208,551

• Package / Case: 208-TFBGA
• Voltage - Supply (vcc/vdd): 1.1 V ~ 1.3 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 180MHz
• Number Of I /o: 10
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Ram Size: 192K x 8
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, I2S, SPI, UART
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935287563551

NXP Semiconductors
LPC3152_3154
Preliminary data sheet
Within most clock domains, the output clocks are again grouped into one or more
subdomains. All output clocks within one subdomain are either all generated by the same
fractional divider or they are connected directly to the base clock. Therefore all output
clocks within one subdomain have the same frequency and all output clocks within one
clock domain are synchronous because they originate from the same base clock
The CGU reference clock is generated by the external crystal. Furthermore the CGU has
several Phase Locked Loop (PLL) circuits to generate clock signals that can be used for
system clocks and/or audio clocks. All clock sources, except the output of the PLLs, can
be used as reference input for the PLLs.
This module has the following features:
•
•
•
•
•
Advanced features to optimize the system for low power:
– All output clocks can be disabled individually for flexible power optimization
– Some modules have automatic clock gating: they are only active when (bus)
– Variable clock scaling for automatic power optimization of the AHB bus (high clock
– Clock wake-up feature: module clocks can be programmed to be activated
Supports three clock sources:
– Reference clock generated by the oscillator with an external crystal.
– Pins I2SRX_BCK0, I2SRX_WS0 are used to input external clock signals (used for
Two PLLs:
– System PLL generates programmable system clock frequency from its reference
– Audio PLL generates programmable audio clock frequency (typically 256 × fs) from
Highly flexible switchbox to distribute the signals from the clock sources to the module
clocks.
– Each clock generated by the CGU is derived from one of the base clocks and
– Each base clock can be programmed to have any one of the clock sources as an
– Fractional dividers can be used to divide a base clock by a fractional number to a
– Fractional dividers support clock stretching to obtain a (near) 50% duty cycle
Register interface to reset all modules under software control.
access to the module is required.
frequency when the bus is active, low clock frequency when the bus is idle).
automatically on the basis of an event detected by the Event Router (see also
Section
activated automatically when a button is pressed.
generating audio frequencies in I
Section
input.
its reference input.
Remark: Both the System PLL and the audio PLL generate their frequencies
based on their (individual) reference clocks. The reference clocks can be
programmed to the oscillator clock or one of the external clock signals.
optionally divided by a fractional divider.
input clock.
lower clock frequency.
output clock.
6.19). For example, all clocks (including the ARM /bus clocks) are off and
6.4).
All information provided in this document is subject to legal disclaimers.
Rev. 0.12 — 27 May 2010
2
S receive / I
2
S transmit slave mode, see also
LPC3152/3154
© NXP B.V. 2010. All rights reserved.
27 of 88