LPC3154FET208,551 NXP Semiconductors, LPC3154FET208,551 Datasheet - Page 21

• Manufacturer Part Number: LPC3154FET208,551
• Description: IC ARM9 MCU USB OTG 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3154FET208,551

• Package / Case: 208-TFBGA
• Voltage - Supply (vcc/vdd): 1.1 V ~ 1.3 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 180MHz
• Number Of I /o: 10
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Ram Size: 192K x 8
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, I2S, SPI, UART
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935287563551

NXP Semiconductors
LPC3152_3154
Preliminary data sheet
6.8 Internal RAM memory
The boot ROM determines the boot mode based on the reset state of the GPIO0, GPIO1,
and GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins
TRST_N and JTAGSEL must be low during power-on reset, see UM10315 JTAG chapter
for details.
Table 9
process fails (e.g. due to tampering with security), the boot code drives pin GPIO3 HIGH.
It is recommended to connect the GPIO3 pin to PSU_STOP, so that the LPC3152/3154
will be powered down and further access prevented when the boot ROM detects an error.
Table 9.
[1]
The ISRAM (Internal Static Memory Controller) module is used as controller between the
AHB bus and the internal RAM memory. The internal RAM memory can be used as
working memory for the ARM processor and as temporary storage to execute the code
that is loaded by boot ROM from external devices such as SPI-flash, NAND flash and
SD/MMC cards.
This module has the following features:
Boot mode
NAND
SPI
DFU
SD/MMC
Reserved 0
NOR flash
UART
Test
•
•
For security reasons this mode is disabled when JTAG security feature is used.
Capacity of 192 kB
Implemented as two independent 96 kB memory banks
shows the various boot modes supported on the LPC3152/3154. If the boot
LPC3152/3154 boot modes
GPIO0 GPIO1 GPIO2 Description
0
0
0
0
1
1
1
1
All information provided in this document is subject to legal disclaimers.
0
0
1
1
0
0
1
1
Rev. 0.12 — 27 May 2010
0
1
0
1
0
1
0
1
Boots from NAND flash. If proper image is not found,
boot ROM will switch to DFU boot mode.
Boot from SPI NOR flash connected to SPI_CS_OUT0. If
proper image is not found, boot ROM will switch to DFU
boot mode.
Device boots via USB using DFU class specification.
Boot ROM searches all the partitions on the
SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image.
If partition table is missing, it will start searching from
sector 0. A valid image is said to be found if a valid image
header is found, followed by a valid image. If a proper
image is not found, boot ROM will switch to DFU boot
mode.
Reserved for testing.
Boot from parallel NOR flash connected to
EBI_NSTCS_1.
Boot ROM tries to download boot image from UART
((115200 – 8 – n –1) assuming 12 MHz FFAST clock).
Boot ROM is testing ISRAM using memory pattern test
and basic functionality of the analog audio block.
Switches to UART boot mode on receiving three ASCI
dots ("...") on UART.
[1]
LPC3152/3154
© NXP B.V. 2010. All rights reserved.
21 of 88