LPC3152FET208,551 NXP Semiconductors, LPC3152FET208,551 Datasheet - Page 66

• Manufacturer Part Number: LPC3152FET208,551
• Description: IC ARM9 MCU USB OTG 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3152FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 10
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, I2S, SPI, UART
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11029
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935287561551

NXP Semiconductors
Table 25.
T
[1]
[2]
[3]
[4]
[5]
[6]
LPC3152_3154
Preliminary data sheet
Symbol Parameter
t
t
t
t
t
t
t
t
h(o)
d(AV)
h(A)
d(QV)
h(Q)
su(D)
h(D)
QZ
amb
Parameters are valid over operating temperature range unless otherwise specified.
All values valid for pads set to high slew rate. VDDE_IOA = VDDE_IOB = 1.8 ± 0.15 V. VDDI = 1.2 ± 0.1 V.
Refer to the LPC3152/3154 user manual for the programming of MPMCDynamicReadConfig and SYSCREG_MPMP_DELAYMODES
registers.
f
t
SYSCREG_MPMP_DELAYMODES register bits 11:6.
t
oper
d(o)
su(D)
=
−
, t
40
= 1 / T
, t
h(o)
h(D)
address valid delay
time
address hold time
data output valid
delay time
data output hold time
data input set-up
time
data input hold time
data output
high-impedance time
°
output hold time
Dynamic characteristics of SDR SDRAM memory interface
, t
C to +85
d(AV)
times are dependent on SYSCREG_MPMP_DELAYMODES register bits 5:0.
CLCL
, t
h(A)
°
, t
C, unless otherwise specified.
d(QV)
, t
h(Q)
times are dependent on MPMCDynamicReadConfig register value and
Conditions
on pin EBI_CKE
on pins
EBI_NRAS_BLOUT,
EBI_NCAS_BLOUT,
EBI_NWE,
EBI_NDYCS
on pins EBI_DQM_1,
EBI_DQM_0_NOE
All information provided in this document is subject to legal disclaimers.
Rev. 0.12 — 27 May 2010
[1][2][3]
[5]
[5]
[5]
[5]
[5]
[6]
[6]
0.13
−0.1
1.7
-
−0.1
-
4
<tbd>
<tbd>
-
Min
-
-
-
-
-
-
-
-
-
-
…continued
Typical
LPC3152/3154
3.6
3.6
5
5
5
9
10
-
-
<T
CLCL
© NXP B.V. 2010. All rights reserved.
Max
66 of 88
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns