P89LPC9241FDH,112 NXP Semiconductors, P89LPC9241FDH,112 Datasheet - Page 44

• Manufacturer Part Number: P89LPC9241FDH,112
• Description: IC 80C51 MCU FLASH 4K 20-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9241FDH,112

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288642112

NXP Semiconductors
P89LPC92X1
Product data sheet
7.28.2 Features
7.28.3 Flash organization
7.28.4 Using flash as data storage
7.28.5 Flash programming and erasing
programming mechanisms. The P89LPC9201/9211/922A1/9241/9251 uses V
supply voltage to perform the Program/Erase algorithms. When voltage supply is lower
than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked.
The program memory consists of two/four/eight 1 kB sectors on the
P89LPC9201/9211/922A1/9241/9251 devices. Each sector can be further divided into
64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page
register is included which allows from 1 byte to 64 bytes of a given page to be
programmed at the same time, substantially reducing overall programming time.
The flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
Four different methods of erasing or programming of the flash are available. The flash
may be programmed or erased in the end-user application (IAP) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock/serial data interface. As shipped from the
factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for
the device to be programmed in circuit through the serial port. The flash may also be
programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verification of code memory
contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire
user code space.
Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash
erase/program is blocked.
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Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP/IAP/ICP.
Internal fixed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program
memory.
Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the flash for each sector.
100,000 typical erase/program cycles for each byte.
10 year minimum data retention.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 December 2010
P89LPC9201/9211/922A1/9241/
8-bit microcontroller with 8-bit ADC
© NXP B.V. 2010. All rights reserved.
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