P89LPC9241FDH,112 NXP Semiconductors, P89LPC9241FDH,112 Datasheet - Page 40

• Manufacturer Part Number: P89LPC9241FDH,112
• Description: IC 80C51 MCU FLASH 4K 20-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9241FDH,112

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288642112

NXP Semiconductors
P89LPC92X1
Product data sheet
7.24 Analog comparators
Two analog comparators are provided on the P89LPC9201/9211/922A1/9241/9251. Input
and output options allow use of the comparators in a number of different configurations.
Comparator operation is such that the output is a logical one (which may be read in a
register and/or routed to a pin) when the positive input (one of two selectable inputs) is
greater than the negative input (selectable from a pin or an internal reference voltage).
Otherwise the output is a zero. Each comparator may be configured to cause an interrupt
when the output value changes.
Fig 12. I
P1.3/SDA
P1.2/SCL
2
C-bus serial interface block diagram
All information provided in this document is subject to legal disclaimers.
OUTPUT
OUTPUT
Rev. 2 — 1 December 2010
FILTER
FILTER
STAGE
STAGE
INPUT
INPUT
P1.3
P1.2
P89LPC9201/9211/922A1/9241/
status bus
overflow
I2SCLH
I2SCLL
I2CON
I2STAT
timer 1
AND SYNC LOGIC
SERIAL CLOCK
BIT COUNTER /
ARBITRATION
GENERATOR
SCL DUTY CYCLE REGISTERS
ADDRESS REGISTER
CONTROL REGISTERS AND
SHIFT REGISTER
DECODER
COMPARATOR
STATUS
STATUS REGISTER
8-bit microcontroller with 8-bit ADC
8
CONTROL
TIMING
LOGIC
AND
I2DAT
8
8
8
ACK
I2ADR
© NXP B.V. 2010. All rights reserved.
CCLK
interrupt
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