AT91SAM7L128-AU Atmel, AT91SAM7L128-AU Datasheet - Page 165
AT91SAM7L128-AU
Manufacturer Part Number
AT91SAM7L128-AU
Description
MCU ARM7 128K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7L128-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
80
Ram Memory Size
6KB
Cpu Speed
36MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
128LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
36 MHz
Operating Supply Voltage
2.5|3.3 V
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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20.2.5.7
20.2.5.8
6257A–ATARM–20-Feb-08
Memory Write Command
Get Version Command
Table 20-13. Set Security Bit Command
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security
bit is to erase the Flash.
In order to erase the Flash, the user must perform the following:
Then it is possible to return to FFPI mode and check that Flash is erased.
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking
can be chained; an internal address buffer is automatically increased.
Table 20-14. Write Command
The Get Version (GVE) command retrieves the version of the FFPI interface.
Table 20-15. Get Version Command
Step
1
2
Step
1
2
3
4
5
...
n
n+1
n+2
n+3
...
Step
1
2
• Power-off the chip
• Power-on the chip with TST = 0 and FWUP =0
• Assert Erase during a period of more than 220 ms
• Power-off the chip
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Handshake Sequence
Write handshaking
Write handshaking
AT91SAM7L128/64 Preliminary
ADDR1
...
ADDR1
DATA
DATA
...
MODE[3:0]
CMDE
ADDR0
DATA
DATA
ADDR0
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
DATA[15:0]
WRAM
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
DATA[15:0]
Version
GVE
DATA[15:0]
SSE
0
165
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