ATSAM3S4AA-AU Atmel, ATSAM3S4AA-AU Datasheet - Page 841

• Manufacturer Part Number: ATSAM3S4AA-AU
• Description: IC MCU 32BIT 256KB FLASH 48LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 34
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Package: 48LQFP
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 9-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

35.14.18 HSMCI Write Protect Status Register
Name:
Address:
Access:
• WP_VS: Write Protection Violation Status
• WP_VSRC: Write Protection Violation SouRCe
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
6500C–ATARM–8-Feb-11
Value
31
23
15
0
1
2
3
–
7
–
RESET
WRITE
NONE
Name
BOTH
30
22
14
HSMCI_WPSR
0x400000E8
Read-only
–
6
–
Description
No Write Protection Violation occurred since the last read of this
register (WP_SR)
Write Protection detected unauthorized attempt to write a control
register had occurred (since the last read.)
Software reset had been performed while Write Protection was
enabled (since the last read).
Both Write Protection violation and software reset with Write
Protection enabled have occurred since the last read.
29
21
13
–
5
–
28
20
12
–
4
–
WP_VSRC
WP_VSRC
27
19
11
–
3
26
18
10
–
2
SAM3S Preliminary
WP_VS
25
17
–
9
1
24
16
–
8
0
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