ATSAM3S4AA-AU Atmel, ATSAM3S4AA-AU Datasheet - Page 728
ATSAM3S4AA-AU
Manufacturer Part Number
ATSAM3S4AA-AU
Description
IC MCU 32BIT 256KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
48KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Package
48LQFP
Device Core
ARM Cortex M3
Family Name
AT91
Maximum Speed
64 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
34
Interface Type
I2C/I2S/SPI/UART/USART/USB
On-chip Adc
9-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ATSAM3S4AA-AU
Manufacturer:
ON
Quantity:
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33.8.6
Name:
Addresses:
Access:
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been
requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
• ENDRX: End of Receiver Transfer
0: The End of Transfer signal from the Receive PDC channel is inactive.
1: The End of Transfer signal from the Receive PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The End of Transfer signal from the Transmit PDC channel is inactive.
1: The End of Transfer signal from the Transmit PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
728
728
PARE
CTS
31
23
15
–
–
7
SAM3S Preliminary
SAM3S Preliminary
USART Channel Status Register
FRAME
DCD
30
22
14
US_CSR
0x40024014 (0), 0x40028014 (1)
Read-only
–
–
6
NACK
OVRE
DSR
29
21
13
–
5
RXBUFF
ENDTX
28
20
12
RI
–
4
TXBUFE
ENDRX
CTSIC
27
19
11
–
3
ITER/UNRE
RXBRK
DCDIC
26
18
10
–
2
TXEMPTY
TXRDY
DSRIC
25
17
–
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
TIMEOUT
MANERR
RXRDY
RIIC
24
16
8
0
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