ATSAM3S4AA-AU Atmel, ATSAM3S4AA-AU Datasheet - Page 690
ATSAM3S4AA-AU
Manufacturer Part Number
ATSAM3S4AA-AU
Description
IC MCU 32BIT 256KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
48KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Package
48LQFP
Device Core
ARM Cortex M3
Family Name
AT91
Maximum Speed
64 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
34
Interface Type
I2C/I2S/SPI/UART/USART/USB
On-chip Adc
9-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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33.7.3.4
690
690
SAM3S Preliminary
SAM3S Preliminary
Manchester Decoder
Figure 33-12. Asynchronous Start Detection
Figure 33-13. Asynchronous Character Reception
When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The
decoder performs both preamble and start frame delimiter detection. One input line is dedicated
to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally indepen-
dent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble
sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addi-
tion, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register.
Depending on the desired application the preamble pattern matching is to be defined via the
RX_PP field in US_MAN. See
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder.
So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start
frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame
delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled dur-
ing one quarter of a bit time to zero, a start bit is detected. See
rejection mechanism applies.
Clock (x16)
Baud Rate
Sampling
Sampling
Sampling
Baud Rate
Example: 8-bit, Parity Enabled
Detection
Clock
RXD
RXD
Start
Clock
RXD
1
1
2
2
samples
3
3
16
4
4
D0
5
5
samples
Figure 33-9
16
6
6
D1
7
Detection
7
Rejection
samples
Start
Start
16
8
0
D2
1
1
samples
for available preamble patterns.
16
2
2
3
3
D3
samples
4
4
16
5
D4
samples
6
16
7
D5
samples
8
16
Figure
9 10 11 12 13 14 15 16
D6
samples
16
33-14. The sample pulse
D7
samples
16
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Parity
Bit
samples
16
Stop
Bit
Sampling
D0
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