ATSAM3S4AA-AU Atmel, ATSAM3S4AA-AU Datasheet - Page 605
ATSAM3S4AA-AU
Manufacturer Part Number
ATSAM3S4AA-AU
Description
IC MCU 32BIT 256KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
48KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Package
48LQFP
Device Core
ARM Cortex M3
Family Name
AT91
Maximum Speed
64 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
34
Interface Type
I2C/I2S/SPI/UART/USART/USB
On-chip Adc
9-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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30.8.5
Name:
Address:
Access:
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR
• RXBUFF: RX Buffer Full
0 = SPI_RCR
1 = Both SPI_RCR
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
TXBUFE
31
23
15
–
–
–
7
SPI Status Register
(1)
or SPI_RNCR
RXBUFF
(1)
and SPI_RNCR
30
22
14
SPI_SR
0x40008010
Read-only
–
–
–
6
(1)
has a value other than 0.
ENDTX
29
21
13
(1)
–
–
–
5
have a value of 0.
ENDRX
28
20
12
–
–
–
4
OVRES
27
19
11
–
–
–
3
UNDES
MODF
(1)
(1)
26
18
10
–
–
2
or SPI_RNCR
or SPI_TNCR
(1)
SAM3S Preliminary
SAM3S Preliminary
(1)
or SPI_RNCR
or SPI_TNCR
TXEMPTY
TDRE
(1)
(1)
25
17
–
–
9
1
.
.
(1)
(1)
.
.
SPIENS
NSSR
RDRF
24
16
–
8
0
605
605
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