DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet - Page 6
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DSPIC30F2020-30I/MM
Manufacturer Part Number
DSPIC30F2020-30I/MM
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-30I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
15MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
135
5.2
Figure 5-2
Enhanced ICSP Program/Verify mode:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
SMPS devices. There is no minimum time requirement
for holding at V
least P16 must elapse before presenting the key
sequence on PGD.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more
hexadecimal format). See
Format”
FIGURE 5-2:
5.3
Exiting Program/Verify mode is done by removing V
from MCLR, as illustrated in
requirement for exit is that an interval P9b should
elapse between the last clock and program signals on
PGC and PGD before removing V
FIGURE 5-3:
DS70284C-page 6
The MCLR pin is briefly driven high, then low.
A 32-bit key sequence is clocked into PGD.
MCLR is then driven high within a specified
period of time and held.
MCLR
V
PGD
PGC
MCLR
V
PGD
PGC
DD
DD
easily
Entering Enhanced ICSP Mode
Exiting Enhanced ICSP Mode
for more information. The device enters
shows the three steps required to enter
IH
. After V
remembered
PGD = Input
P6
ENTERING ENHANCED ICSP™ MODE
EXITING ENHANCED
ICSP™ MODE
DD
IH
V
is removed, an interval of at
P9b
in the case of dsPIC30F
IH
Appendix A: “Hex File
as
P12
Figure
IH
P15
V
P16
.
IH
0x4D434850
V
5-3. The only
b31
IH
0
b30
1
Program/Verify Entry Code = 0x4D434850
b29
IH
0
in
IH
,
b28
P1B
0
P1A
b27
Program/Verify mode only if the key sequence is valid.
The Most Significant bit (MSb) of the most significant
nibble must be shifted in first.
The key data is clocked on the rising edge of the clock
PGC. Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode has to be maintained. An interval
of at least time P17 and P7 must elapse before
presenting data on PGD. Signals appearing on PGD
before P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
1
5.4
Before a chip can be programmed, it must be erased.
The Bulk Erase command (ERASEB) is used to perform
this task. Executing this command with the MS
command field set to 0x3 erases all code memory and
code-protect Configuration bits. The Chip Erase
process sets all bits in these three memory regions to ‘1’.
Since code protection Configuration bits are not
erasable, they must be manually set to ‘1’ using
multiple PROGC commands. One PROGC command
must be sent for each Configuration register (see
Section 5.7 “Configuration Bits
Note:
Note:
...
Chip Erase
b3
0
When in Enhanced ICSP mode, the SPI
output pin, SDO1, will toggle while the
device is being programmed.
The Device ID registers cannot be erased.
These registers remain intact after a Chip
Erase is performed.
b2
0
b1
0
© 2010 Microchip Technology Inc.
V
IH
b0
0
P17
Programming”).
P7
IH
must be