DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet - Page 33
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DSPIC30F2020-30I/MM
Manufacturer Part Number
DSPIC30F2020-30I/MM
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-30I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
15MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
135
11.7
The FOSC, FWDT, FPOR and FICD registers are not
erasable. It is recommended that all Configuration
registers can be set to a default value after erasing pro-
gram memory. The FWDT, FPOR and FICD registers
can be set to a default all ‘1’s value by programming
0xFFFF to each register. Since these registers contain
unimplemented bits that read as ‘0’, the default values
shown in
The recommended default FOSC value is 0xC100,
which selects the FRC clock oscillator setting.
The FBS and FGS Configuration registers are special
since they enable code protection for the device. For
security purposes, once the bits in these registers are pro-
grammed to ‘0’ (to enable code protection), they can only
be set back to ‘1’ by performing a Bulk Erase as described
in
using a Segment Erase operation. Programming the FBS
or FGS Configuration register bits from a ‘0’ to ‘1’ is not
possible, but they can be programmed from a ‘1’ to a ‘0’
to enable code protection.
Table 11-7
clearing the Configuration registers. In Step 1, the
Reset vector is exited. In Step 2, the write pointer (W7)
is loaded with 0x0000, which is the original destination
address (in TBLPAG 0xF8 of program memory). In
Step 3, the NVMCON is set to program one
Configuration register. In Step 4, the TBLPAG register
TABLE 11-7:
© 2010 Microchip Technology Inc.
Step 1: Exit the Reset vector.
0000
0000
0000
Step 2: Initialize the write pointer (W7) for the TBLWT instruction.
0000
Step 3: Set the NVMCON to program 1 Configuration register.
0000
0000
Step 4: Initialize the TBLPAG register.
0000
0000
Step 5: Load the Configuration register data to W6.
0000
Step 6: Write the Configuration register data to the write latch and increment the write pointer.
0000
0000
0000
Step 7: Unlock the NVMCON for programming.
0000
0000
0000
0000
Section 11.5 “Bulk Erasing Program
Command
(Binary)
Writing Configuration Memory
Table 11-6
shows the ICSP programming details for
040100
040100
000000
200007
24008A
883B0A
200F80
880190
2xxxx0
BB1B86
000000
000000
200558
883B38
200AA9
883B39
SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS
will be read instead of 0xFFFF.
(Hex)
Data
GOTO 0x100
GOTO 0x100
NOP
MOV
MOV
MOV
MOV
MOV
MOV
TBLWTL W6, [W7++]
NOP
NOP
MOV
MOV
MOV
MOV
Memory”, or by
#0x0000, W7
#0x4008, W10
W10, NVMCON
#0xF8, W0
W0, TBLPAG
#<CONFIG_VALUE>, W6
#0x55, W8
W8, NVMKEY
#0xAA, W9
W9, NVMKEY
is initialized to 0xF8 for writing to the Configuration
registers. In Step 5, the value to write to each
Configuration register (0xFFFF) is loaded to W6. In
Step 6, the Configuration register data is written to the
write latch using the TBLWTL instruction. In Steps 7 and
8, the NVMCON is unlocked for programming and the
programming cycle is initiated, as described in
Section 11.4 “Flash Memory Programming in ICSP
Mode”. In Step 9, the internal PC is set to 0x100 as a
safety measure to prevent the PC from incrementing
into unimplemented memory. Finally, Steps 3-9 are
repeated six times until all seven Configuration
registers are programmed.
TABLE 11-6:
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
0xF8000E
Address
Description
FBS
RESERVED
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
DEFAULT CONFIGURATION
REGISTER VALUES
Register
0x000F
0x0000
0x0007
0x0003
0x00E7
0x00DF
0x0007
0x0083
DS70284C-page 33
Default Value