DSPIC33FJ64GP710-E/PT Microchip Technology, DSPIC33FJ64GP710-E/PT Datasheet - Page 129
![IC DSPIC MCU/DSP 64K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ64GP710-E/PT
Manufacturer Part Number
DSPIC33FJ64GP710-E/PT
Description
IC DSPIC MCU/DSP 64K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
Specifications of DSPIC33FJ64GP710-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TFQFP
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ64GP206-IPT PDF datasheet #2
- DSPIC33FJ64GP206-IPT PDF datasheet #3
- Current page: 129 of 322
- Download datasheet (5Mb)
8.0
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33FJXXXGPX06/X08/X10 peripherals that
can utilize DMA are listed in Table 8-1 along with their
associated Interrupt Request (IRQ) numbers.
TABLE 8-1:
© 2009 Microchip Technology Inc.
INT0
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer2
Timer3
SPI1
SPI2
UART1 Reception
UART1 Transmission
UART2 Reception
UART2 Transmission
ADC1
ADC2
DCI
ECAN1 Reception
ECAN1 Transmission
ECAN2 Reception
ECAN2 Transmission
Note:
intervention.
DIRECT MEMORY ACCESS
(DMA)
This data sheet summarizes the features
of the dsPIC33FJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 22.
“Direct
(DS70182) in the “dsPIC33F Family
Reference Manual”, which is available
from
(www.microchip.com).
Peripheral
PERIPHERALS WITH DMA
SUPPORT
the
Memory
The
Microchip
DMA
Access
dsPIC33FJXXXGPX06/X08/X10
controller
IRQ Number
web
10
33
12
30
31
13
21
60
34
70
55
71
11
0
1
5
2
6
7
8
(DMA)”
site
can
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
• Indirect Addressing of DMA RAM locations with or
• Peripheral Indirect Addressing – In some
• One-Shot Block Transfers – Terminating DMA
• Continuous Block Transfers – Reloading DMA
• Ping-Pong Mode – Switching between two DMA
• Automatic or manual initiation of block transfers
• Each channel can select from 20 possible
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
RAM to peripheral.
without automatic post-increment.
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral.
transfer after one block transfer.
RAM buffer start address after every block
transfer is complete.
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
sources of data sources or destinations.
DS70286C-page 127
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