ATXMEGA32A4-CU Atmel, ATXMEGA32A4-CU Datasheet - Page 73
ATXMEGA32A4-CU
Manufacturer Part Number
ATXMEGA32A4-CU
Description
MCU AVR 32+4 FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA32A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA32x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 1 Channel
On-chip Dac
2 bit, 1 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Price
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6.8.2
8077H–AVR–12/09
CHnCTRL – Event Channel n Control Register
.
• Bit 7 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 6:5 - QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals where a valid
index signal is recognized and the counter index data event is given according to
page
nal is used.
These bits are only available for CH0CTRL, CH2CTRL and CH4CTRL
Table 6-5.
• Bit 4 - QDIEN: Quadrature Decode Index Enable
When this bit is set the event channel will be used as QDEC index source, and the index data
event will be enabled.
These bit is only available for CH0CTRL, CH2CTRL and CH4CTRL.
• Bit 3 - QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
These bits is only available for CH0CTRL, CH2CTRL and CH4CTRL.
• Bit 2:0 - DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event
channel only when the event source has been active and sampled with the same level for a a
number of peripheral clock for the number of cycles as defined by DIGFILT.
Bit
Read/Write
Initial Value
QDIRM[1:0]
0
0
1
1
73. These bits is only needed to set when a quadrature encoed with a connected index sig-
0
1
0
1
QDIRM Bit Settings
7
R
0
-
Index Recognition State
{QDPH0, QDPH90} = 0b00
{QDPH0, QDPH90} = 0b01
{QDPH0, QDPH90} = 0b10
{QDPH0, QDPH90} = 0b11
R/W
6
0
QDIRM[1:0]
R/W
5
0
QDIEN
R/W
4
0
QDEN
R/W
3
0
R/W
2
0
DIGFILT[2:0]
R/W
1
0
XMEGA A
R
0
0
Table 6-5 on
CHnCTRL
73
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