ATXMEGA32A4-CU Atmel, ATXMEGA32A4-CU Datasheet - Page 202
ATXMEGA32A4-CU
Manufacturer Part Number
ATXMEGA32A4-CU
Description
MCU AVR 32+4 FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA32A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA32x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 1 Channel
On-chip Dac
2 bit, 1 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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18.3.10
18.3.11
18.3.12
18.3.13
18.3.14
8077H–AVR–12/09
PER2 - Period Register 2
PER1 - Period Register 1
PER0 - Period Register 0
COMP3 - Compare Register 3
COMP2 - Compare Register 2
The COMP0, COMP1, COMP2 and COMP3 registers represents the 32-bit value COMP. COMP
is constantly compared with the counter value (CNT). A compare match will set the COMPIF in
the INTFLAGS register, and the optional interrupt is generated.
If the COMP value is higher than the PER value, no RTC Compare Match interrupt requests or
events will be generated
After writing the high byte of the COMP register, the condition for setting OVFIF and COMPIF,
as well as the Overflow and Compare Match Wakeup condition, will be disabled for the following
two RTC clock cycles.
Bit
+0x0A
Read/Write
Reset Value
Bit
+0x09
Read/Write
Reset Value
Bit
+0x08
Read/Write
Reset Value
Bit
+0x0F
Read/Write
Reset Value
Bit
+0x0E
Read/Write
Reset Value
R/W
R/W
R/W
R/W
R/W
7
7
7
7
7
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
6
6
6
6
6
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
5
5
5
5
5
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
4
4
4
4
COMP[31:24]
4
COMP[23:16]
0
0
0
0
0
PER[23:16]
PER[15:8]
PER[7:0]
R/W
R/W
R/W
R/W
R/W
3
3
3
3
3
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
0
0
0
0
0
XMEGA A
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
COMP3
COMP2
PER2
PER1
PER0
202
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