PIC18F87K22-I/PTRSL Microchip Technology, PIC18F87K22-I/PTRSL Datasheet - Page 218
PIC18F87K22-I/PTRSL
Manufacturer Part Number
PIC18F87K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 80TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F87K22-I/PTRSL
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 218 of 548
- Download datasheet (5Mb)
PIC18F87K22 FAMILY
FIGURE 16-5:
16.5.5
When Timer3/5/7 gate value status is utilized, it is
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
DS39960B-page 218
Timer3/5/7
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
TxGGO/
TxGVAL
TxG_IN
TxGTM
TxCKI
TIMER3/5/7 GATE VALUE STATUS
TIMER3/5/7 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
N
Cleared by Software
Counting Enabled on
Rising Edge of TxG
Set by Software
Preliminary
N + 1
Falling Edge of TxGVAL
N + 2
16.5.6
When the Timer3/5/7 gate event interrupt is enabled, it
is possible to generate an interrupt upon the comple-
tion of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
Set by Hardware on
N + 3
TIMER3/5/7 GATE EVENT
INTERRUPT
2010 Microchip Technology Inc.
N + 4
Cleared by Hardware on
Falling Edge of TxGVAL
Cleared by
Software
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