ATMEGA1284P-AUR Atmel, ATMEGA1284P-AUR Datasheet - Page 71

MCU AVR 128KB FLASH 20MHZ 44TQFP

ATMEGA1284P-AUR

Manufacturer Part Number
ATMEGA1284P-AUR
Description
MCU AVR 128KB FLASH 20MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA1284P-AUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA1284P-AUR
Manufacturer:
Atmel
Quantity:
10 000
12.2.6
12.2.7
12.2.8
8272A–AVR–01/10
PCMSK3 – Pin Change Mask Register 3
PCMSK2 – Pin Change Mask Register 2
PCMSK1 – Pin Change Mask Register 1
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 7:0 – PCINT31:24: Pin Change Enable Mask 31:24
Each PCINT31:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT31:24 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT31..24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23..16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x73)
Read/Write
Initial Value
Bit
(0x6D)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
PCINT31
PCINT23
PCINT15
R/W
R/W
R/W
7
0
7
0
7
0
PCINT30
PCINT22
PCINT14
R/W
R/W
R/W
6
0
6
0
6
0
PCINT29
PCINT21
PCINT13
R/W
R/W
R/W
5
0
5
0
5
0
PCINT28
PCINT20
PCINT12
R/W
R/W
R/W
4
0
4
0
4
0
PCINT27
PCINT19
PCINT11
R/W
R/W
R/W
3
0
3
0
3
0
PCINT26
PCINT18
PCINT10
R/W
R/W
R/W
2
0
2
0
2
0
PCINT25
PCINT17
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
PCINT24
PCINT16
PCINT8
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK3
PCMSK2
PCMSK1
71

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