ATMEGA1284P-AUR Atmel, ATMEGA1284P-AUR Datasheet - Page 262

MCU AVR 128KB FLASH 20MHZ 44TQFP

ATMEGA1284P-AUR

Manufacturer Part Number
ATMEGA1284P-AUR
Description
MCU AVR 128KB FLASH 20MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA1284P-AUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA1284P-AUR
Manufacturer:
Atmel
Quantity:
10 000
Figure 23-1. Block Diagram
8272A–AVR–01/10
TDI
TDO
TCK
TMS
CONTROLLER
M
U
X
TAP
DEVICE BOUNDARY
INSTRUCTION
BREAKPOINT
SCAN CHAIN
REGISTER
REGISTER
REGISTER
BYPASS
ID
• TCK: Test Clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the
TAP controller is in reset. When programmed, the input TAP signals are internally pulled high
and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this
fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
(Scan Chains).
DECODER
ADDRESS
JTAG PROGRAMMING
MEMORY
FLASH
AND CONTROL
BREAKPOINT
OCD STATUS
INTERFACE
UNIT
Address
Data
I/O PORT 0
I/O PORT n
INTERNAL
FLOW CONTROL
CHAIN
SCAN
UNIT
BOUNDARY SCAN CHAIN
PC
Instruction
JTAG / AVR CORE
COMMUNICATION
PERIPHERAL
INTERFACE
AVR CPU
DIGITAL
UNITS
PERIPHERIAL
ANALOG
UNITS
Control & Clock lines
Analog inputs
262

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