ATMEGA1284P-MUR Atmel, ATMEGA1284P-MUR Datasheet - Page 261

MCU AVR 128KB FLASH 20MHZ 44VQFN

ATMEGA1284P-MUR

Manufacturer Part Number
ATMEGA1284P-MUR
Description
MCU AVR 128KB FLASH 20MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA1284P-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Quantity
Price
Part Number:
ATMEGA1284P-MUR
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23. JTAG Interface and On-chip Debug System
23.1
23.2
23.3
8272A–AVR–01/10
Features
Overview
TAP – Test Access Port
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
• Testing PCBs by using the JTAG Boundary-scan capability
• Programming the non-volatile memories, Fuses and Lock bits
• On-chip debugging
A brief description is given in the following sections. Detailed descriptions for Programming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections
ming via the JTAG Interface” on page 314
267, respectively. The On-chip Debug support is considered being private JTAG instructions,
and distributed within ATMEL and to selected third party vendors only.
Figure 23-1
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG
instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used
for board-level testing. The JTAG Programming Interface (actually consisting of several physical
and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port – TAP. These pins are:
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
164A/164PA/324A/324PA/644A/644PA/1284/1284P
machine.
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
shows a block diagram of the JTAG interface and the On-chip Debug system. The
and
®
”IEEE 1149.1 (JTAG) Boundary-scan” on page
”Program-
261

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