ATMEGA1284P-MUR Atmel, ATMEGA1284P-MUR Datasheet - Page 259

• Manufacturer Part Number: ATMEGA1284P-MUR
• Description: MCU AVR 128KB FLASH 20MHZ 44VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1284P-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.9.3
ADLAR = 0
ADLAR = 1
22.9.4
8272A–AVR–01/10
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
Table 22-5.
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x7B)
Read/Write
Initial Value
254.
ADPS2
1
1
1
1
ADC Prescaler Selections (Continued)
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
R
7
–
0
ACME
ADC6
ADC8
ADC0
R/W
14
14
R
R
R
R
ADPS1
–
6
0
0
6
0
0
6
0
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
R
–
5
0
0
–
5
0
0
5
–
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
R
4
–
0
ADPS0
0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
R
3
–
0
ADTS2
ADC2
ADC4
R/W
10
10
R
R
R
R
–
2
0
0
–
2
0
0
2
0
”ADC Conversion Result” on
ADTS1
ADC9
ADC1
ADC3
Division Factor
R/W
R
R
R
R
9
1
0
0
9
–
1
0
0
1
0
128
16
32
64
ADTS0
ADC8
ADC0
ADC2
R/W
R
R
R
R
8
0
0
0
8
–
0
0
0
0
0
ADCSRB
ADCH
ADCH
ADCL
ADCL
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