ATMEGA1284P-MUR Atmel, ATMEGA1284P-MUR Datasheet - Page 199

MCU AVR 128KB FLASH 20MHZ 44VQFN

ATMEGA1284P-MUR

Manufacturer Part Number
ATMEGA1284P-MUR
Description
MCU AVR 128KB FLASH 20MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA1284P-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA1284P-MUR
Manufacturer:
FREESCALE
Quantity:
593
19. USART in SPI Mode
19.1
19.2
19.3
8272A–AVR–01/10
Features
Overview
Clock Generation
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation.
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
control logic is disabled. The USART RX and TX control logic is replaced by a common SPI
transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the
control registers changes when using MSPIM.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-
ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations, see
Table 19-1.
Note:
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Operating Mode
Synchronous Master
mode
Full Duplex, Three-wire Synchronous Data Transfer
Master Operation
Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
LSB First or MSB First Data Transfer (Configurable Data Order)
Queued Operation (Double Buffered)
High Resolution Baud Rate Generator
High Speed Operation (fXCKmax = fCK/2)
Flexible Interrupt Generation
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Equations for Calculating Baud Rate Register Setting
Table
19-1:
Equation for Calculating Baud
BAUD
=
Rate
-------------------------------------- -
2 UBRRn
(
(1)
f
OSC
+
1
)
Equation for Calculating UBRRn
UBRRn
Value
=
------------------- - 1
2BAUD
f
OSC
199

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