ATMEGA1284P-MUR Atmel, ATMEGA1284P-MUR Datasheet - Page 159

• Manufacturer Part Number: ATMEGA1284P-MUR
• Description: MCU AVR 128KB FLASH 20MHZ 44VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1284P-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.11.7
8272A–AVR–01/10
TIMSK2 – Timer/Counter2 Interrupt Mask Register
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf-
fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a
32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected.
Note that the crystal Oscillator will only run when this bit is zero.
• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk
written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-
lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,
OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.
When OCR2B has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
When TCCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new
value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.
When TCCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new
value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.
When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A
and TCCR2B the value in the temporary storage register is read.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x70)
Read/Write
R
7
–
R
6
–
R
5
–
R
4
–
R
3
–
OCIE2B
R/W
2
OCIE2A
R/W
1
TOIE2
I/O
R/W
0
. When AS2 is
TIMSK2
159