ATMEGA1284P-MUR Atmel, ATMEGA1284P-MUR Datasheet - Page 139

MCU AVR 128KB FLASH 20MHZ 44VQFN

ATMEGA1284P-MUR

Manufacturer Part Number
ATMEGA1284P-MUR
Description
MCU AVR 128KB FLASH 20MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA1284P-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Quantity
Price
Part Number:
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Quantity:
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15.11.9
8272A–AVR–01/10
TIFR1 – Timer/Counter1 Interrupt Flag Register
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “10.3” on page
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P,
and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4:3 – Res: Reserved Bits
These bits are unused bits in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P,
and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to
Flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
0x16 (0x36)
Read/Write
Initial Value
R
7
0
R
6
0
56.) is executed when the TOV1 Flag, located in TIFR1, is set.
ICF1
R/W
5
0
R
4
0
R
3
0
Table 15-5 on page 135
OCF1B
R/W
2
0
OCF1A
R/W
1
0
TOV1
R/W
0
0
for the TOV1
TIFR1
139

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