ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 209
ATMEGA64M1-AU
Manufacturer Part Number
ATMEGA64M1-AU
Description
IC MCU AVR 64K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64M1-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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20.5.6.3
20.5.7
20.5.7.1
8209D–AVR–11/10
Data Length
Handling LBT[5:0]
Data Length in LIN 2.1
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be
reset to 32 for the next header.
The LINBTR register can be used to re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
LDISR bit of LINBTR register is used to:
Note that the LENA bit of LINCR register is important for this handling (see
Figure 20-8. Handling LBT[5:0]
Section 20.4.6 “LIN Commands” on page 203
the LRXDL[3..0] or LTXDL[3..0] fields of LINDLR register before receiving or transmitting a
response.
In the case of Tx Response the LRXDL[3..0] will be used by the hardware to count the number of
bytes already successfully sent.
In the case of Rx Response the LTXDL[3..0] will be used by the hardware to count the number of
bytes already successfully received.
If an error occurs, this information is useful to the programmer to recover the LIN messages.
• To enable the setting of LBT[5:0] (to manually adjust the baud rate especially in the case of
• Disable the re-synchronization in LIN Slave Mode for test purposes
• If LTXDL[3..0]=0 only the CHECKSUM will be sent
• If LRXDL[3..0]=0 the first byte received will be interpreted as the CHECKSUM
• If LTXDL[3..0] or LRXDL[3..0] >8, values will be forced to 8 after the command setting and
UART mode). A minimum of 8 is required for LBT[5:0] due to the sampling operation
before sending or receiving of the first byte
=1
Write in LINBTR register
(LINCR bit 4)
LENA ?
Enable re-synch. in LIN mode
LBT[5..0] forced to 0x20
LDISR forced to 0
=0
LDISR
to write
=0
describes how to set or how are automatically set
ATmega16M1/32M1/64M1
=1
Disable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
LDISR forced to 1
(LBT[5..0]
min
Figure
=8)
20-8).
209
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