ATMEGA3250PV-10AUR Atmel, ATMEGA3250PV-10AUR Datasheet - Page 102
ATMEGA3250PV-10AUR
Manufacturer Part Number
ATMEGA3250PV-10AUR
Description
MCU AVR 32K FLASH 10MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA3250P-20AU.pdf
(364 pages)
Specifications of ATMEGA3250PV-10AUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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14.10 Register Description
14.10.1
102
ATmega325P/3250P
TCCR0A – Timer/Counter Control Register A
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written
when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0A output is changed according
to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is
the value present in the COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 14-2.
Note:
• Bit 5:4 – COM0A1:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
Bit
0x24 (0x44)
Read/Write
Initial Value
Mode
0
1
2
3
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
94.
WGM01
(CTC0)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
Waveform Generation Mode Bit Description
FOC0A
W
7
0
WGM00
(PWM0)
WGM00
0
1
0
1
R/W
6
0
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
COM0A1
R/W
5
0
COM0A0
R/W
4
0
WGM01
R/W
3
0
TOP
0xFF
0xFF
OCR0A
0xFF
Table 14-2
(1)
CS02
R/W
2
0
Immediate
BOTTOM
Update of
OCR0A at
TOP
Immediate
and
CS01
R/W
1
0
”Modes of Operation”
CS00
R/W
TOV0 Flag Set
on
MAX
BOTTOM
MAX
MAX
0
0
8023F–AVR–07/09
TCCR0A
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