ATMEGA16-16AU SL383 Atmel, ATMEGA16-16AU SL383 Datasheet - Page 148

IC MCU 8BIT 16KB FLASH 44TQFP

ATMEGA16-16AU SL383

Manufacturer Part Number
ATMEGA16-16AU SL383
Description
IC MCU 8BIT 16KB FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA16-16AU SL383

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Synchronous Clock
Operation
Frame Formats
2466T–AVR–07/10
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
Figure 71. Synchronous Mode XCK Timing.
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As
ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 72
optional.
Figure 72. Frame Formats
St
(n)
P
Sp
1 start bit
5, 6, 7, 8, or 9 data bits
no, even or odd parity bit
1 or 2 stop bits
(IDLE)
UCPOL = 1
UCPOL = 0
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
illustrates the possible combinations of the frame formats. Bits inside brackets are
St
RxD / TxD
RxD / TxD
0
XCK
XCK
Figure 71
1
2
shows, when UCPOL is zero the data will be changed at ris-
3
4
FRAME
[5]
[6]
[7]
[8]
Sample
Sample
[P]
Sp1 [Sp2] (St / IDLE)
ATmega16(L)
148

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