ATMEGA48A-AU Atmel, ATMEGA48A-AU Datasheet - Page 177

IC MCU AVR 4K FLASH 32TQFP

ATMEGA48A-AU

Manufacturer Part Number
ATMEGA48A-AU
Description
IC MCU AVR 4K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
TWI, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48A-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA48A-AUR
Manufacturer:
Atmel
Quantity:
10 000
19. USART0
19.1
19.2
8271C–AVR–08/10
Features
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
The USART0 can also be used in Master SPI mode, see “USART in SPI Mode” on page 205.
The Power Reduction USART bit, PRUSART0, in
must be disabled by writing a logical zero to it.
A simplified block diagram of the USART Transmitter is shown in
accessible I/O Registers and I/O pins are shown in bold.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
”Minimizing Power Consumption” on page 42
Figure 19-1 on page
178. CPU
177

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