AT90PWM316-16SUR Atmel, AT90PWM316-16SUR Datasheet - Page 215

• Manufacturer Part Number: AT90PWM316-16SUR
• Description: MCU AVR 16K FLASH 16MHZ 32-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM316-16SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.3.1
19.3.3.2
7710E–AVR–08/10
Manchester frame
Manchester decoder
Encoder Clock
Manchester Data
Binary Data
Figure 19-2. Manchester Bi-phase levels
The USART supports Manchester encoded frames with the following characteristics:
Figure 19-3. Manchester Frame example
When configured in Manchester mode, the EUSART receiver is able to receive serial frame
using a 17-bit shift register, an edge detector and several data/control registers. The Manchester
decoder receives a frame from the RxD pin of the EUSART interface and loads the received
data in the EUSART data register (UDR and EUDR).
The bit order of the data bits in the frame is configurable to handle MSB or LSB first.
The polarity of the bi-phase start is not configurable. The start bit a logical ‘1’ (rising edge at bit
center).
The polarity of the stop bits is not configurable, the interface allows to read the 2 stops bits value
by software.
The Manchester decoder is enable when the EUSART is configured in Manchester mode and
the RXEN of USCRB set (global USART receive enable).
• One start bit Manchester encoded (logical ‘1’)
• 5, 6, 7, 8, 9, 13, 14,15,16,17 data bits in transmission or reception (MSB or LSB first)
• The number of data bit in a frame is independently configurable in reception and transmission
• One or Two stop bits (level encoded)
mode.
Start
Bit
1 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0
Logical 0
(up to 17 data bit)
Data Bits
Logical 1
AT90PWM216/316
Stop
Bits
215