AT90PWM316-16SUR Atmel, AT90PWM316-16SUR Datasheet - Page 183
![MCU AVR 16K FLASH 16MHZ 32-SOIC](/photos/7/29/72992/313-32-soic_sml.jpg)
AT90PWM316-16SUR
Manufacturer Part Number
AT90PWM316-16SUR
Description
MCU AVR 16K FLASH 16MHZ 32-SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM216-16SU.pdf
(359 pages)
Specifications of AT90PWM316-16SUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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17.2.6
17.3
7710E–AVR–08/10
Data Modes
SPI Data Register – SPDR
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
17-3
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 17-2
Table 17-5.
Figure 17-3. SPI Transfer Format with CPHA = 0
Bit
Read/Write
Initial Value
and
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
Figure
and
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
CPOL Functionality
SS
SPD7
Table
MSB first (DORD = 0)
LSB first (DORD = 1)
R/W
17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-
7
X
17-3, as done below:
SPD6
R/W
X
6
MSB
LSB
Sample (Falling)
SPD5
Sample (Rising)
R/W
Leading Edge
Setup (Falling)
Setup (Rising)
5
X
Bit 6
Bit 1
SPD4
R/W
X
4
Bit 5
Bit 2
SPD3
R/W
3
X
Bit 4
Bit 3
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing eDge
SPD2
Bit 3
Bit 4
R/W
AT90PWM216/316
X
2
Bit 2
Bit 5
SPD1
R/W
1
X
Bit 1
Bit 6
SPD0
R/W
X
0
SPI Mode
LSB
MSB
Undefined
0
1
2
3
SPDR
Figure
183
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