PIC16F688-E/ST Microchip Technology, PIC16F688-E/ST Datasheet - Page 99
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PIC16F688-E/ST
Manufacturer Part Number
PIC16F688-E/ST
Description
IC MCU FLASH 4KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-EP.pdf
(174 pages)
Specifications of PIC16F688-E/ST
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
14-TSSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
256 B
Height
0.9 mm
Length
5 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
4.4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
10.5
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the RC4/C2OUT/TX/CK pin
(instead of being supplied internally in Master mode).
This allows the device to transfer or receive data while
in any Low-power mode.
10.5.1
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 10-9:
2004 Microchip Technology Inc.
Legend:
Addr
0Ch
8Ch
11h
12h
13h
14h
15h
16h
17h
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
PIR1
BAUDCTL ABDOVF
SPBRGH USART Baud Rate High Generator
SPBRG
RCREG
TXREG
TXSTA
RCSTA
PIE1
USART Synchronous Slave Mode
Name
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.
USART SYNCHRONOUS SLAVE
TRANSMIT
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
CSRC
SPEN
Bit 7
EEIF
EEIE
RCIDL
ADIE
Bit 6
ADIF
RX9
TX9
TXEN
SREN
RCIF
RCIE
Bit 5
—
SCKP
SYNC
CREN
Bit 4
C2IF
C2IE
Preliminary
ADDEN
SENDB
BRG16
Bit 3
C1IF
C1IE
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
OSFIF
OSFIE
BRGH
FERR
Bit 2
—
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TRMT
OERR
WUE
TXIE
Bit 1
TXIF
TMR1IF
TMR1IE
ABDEN
RX9D
TX9D
Bit 0
PIC16F688
0000 0000
00-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000X
0000 0000
POR, BOD
Value on
DS41203B-page 97
0000 0000
00-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000X
0000 0000
Value on
all other
Resets