PIC16F688-E/ST Microchip Technology, PIC16F688-E/ST Datasheet - Page 73
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PIC16F688-E/ST
Manufacturer Part Number
PIC16F688-E/ST
Description
IC MCU FLASH 4KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-EP.pdf
(174 pages)
Specifications of PIC16F688-E/ST
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
14-TSSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
256 B
Height
0.9 mm
Length
5 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
4.4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
9.0
Data EEPROM memory is readable and writable and
the Flash program memory is readable during normal
operation (full V
directly mapped in the register file space. Instead, they
are indirectly addressed through the Special Function
Registers. There are six SFRs used to access these
memories:
• EECON1
• EECON2
• EEDAT
• EEDATH
• EEADR
• EEADRH
When interfacing the data memory block, EEDAT holds
the 8-bit data for read/write, and EEADR holds the
address of the EE data location being accessed. This
device has 256 bytes of data EEPROM with an address
range from 0h to 0FFh.
When interfacing the program memory block, the
EEDAT and EEDATH registers form a 2-byte word that
holds the 14-bit data for read/write, and the EEADR
and EEADRH registers form a 2-byte word that holds
the 12-bit address of the EEPROM location being
accessed. This device has 4K words of program
EEPROM with an address range from 0h to 0FFFh.
The program memory allows one word reads.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory
and read the program memory. When code-protected,
the device programmer can no longer access data or
program memory.
Additional information on the data EEPROM is
available in the “PICmicro
Reference Manual” (DS33023).
2004 Microchip Technology Inc.
DATA EEPROM AND FLASH
PROGRAM MEMORY
CONTROL
DD
range). These memories are not
®
Mid-Range MCU Family
Preliminary
9.1
The EEADR and EEADRH registers can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 4K words of program EEPROM.
When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is written to the EEADR register. When selecting a
data address value, only the LSB of the address is
written to the EEADR register.
9.1.1
EECON1 is the control register for EE memory
accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, as it is
when reset, any subsequent operations will operate on
the data memory. When set, any subsequent opera-
tions will operate on the program memory. Program
memory can only be read.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
data EEPROM. On power-up, the WREN bit is clear.
The WRERR bit is set when a write operation is
interrupted by a MCLR or a WDT Time-out Reset
during normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDAT and EEADR registers.
Interrupt flag bit EEIF (PIR1<7>), is set when write is
complete. It must be cleared in the software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
EEADR and EEADRH Registers
EECON1 AND EECON2 REGISTERS
PIC16F688
DS41203B-page 71