ATTINY24A-MMH Atmel, ATTINY24A-MMH Datasheet - Page 138
ATTINY24A-MMH
Manufacturer Part Number
ATTINY24A-MMH
Description
MCU AVR 2K FLASH 20MHZ 20VQFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24A-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 20 Channel
For Use With
ATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.6
16.6.1
138
Changing Channel or Reference Selection
ATtiny24A/44A/84A
ADC Input Channels
For a summary of conversion times, see
Table 16-1.
The MUX[5:0] and REFS[1:0] bits in the ADMUX Register are single buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channels and
reference selection only takes place at a safe point during the conversion. The channel and ref-
erence selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and reference selection is locked to ensure a sufficient sampling time for the
ADC. Continuous updating resumes in the last ADC clock cycle before the conversion com-
pletes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC
clock edge after ADSC is written. The user is thus advised not to write new channel or reference
selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
Condition
First conversion
Normal conversions
Auto Triggered conversions
Free Running conversion
• When ADATE or ADEN is cleared.
• During conversion, minimum one ADC clock cycle after the trigger event.
• After a conversion, before the Interrupt Flag used as trigger source is cleared.
• In Single Conversion mode, always select the channel before starting the conversion. The
• In Free Running mode, always select the channel before starting the first conversion. The
channel selection may be changed one ADC clock cycle after writing one to ADSC. However,
the simplest method is to wait for the conversion to complete before changing the channel
selection.
channel selection may be changed one ADC clock cycle after writing one to ADSC. However,
the simplest method is to wait for the first conversion to complete, and then change the
ADC Conversion Time
Sample & Hold (Cycles from
Start of Conversion)
Table
13.5
1.5
2.5
2
16-1.
Conversion Time (Cycles)
13.5
25
13
14
8183C–AVR–03/11
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