ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 97
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ATTINY4-TSHR
Manufacturer Part Number
ATTINY4-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY4-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
6SOT-23
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY4-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
14. Programming interface
14.1
14.2
14.3
8127D–AVR–02/10
Features
Overview
Physical Layer of Tiny Programming Interface
•
•
The Tiny Programming Interface (TPI) supports external programming of all Non-Volatile Memo-
ries (NVM). Memory programming is done via the NVM Controller, by executing NVM controller
commands as described in
The Tiny Programming Interface (TPI) provides access to the programming facilities. The inter-
face consists of two layers: the access layer and the physical layer. The layers are illustrated in
Figure
Figure 14-1. The Tiny Programming Interface and Related Internal Interfaces
Programming is done via the physical interface. This is a 3-pin interface, which uses the RESET
pin as enable, the TPICLK pin as the clock input, and the TPIDATA pin as data input and output.
NVM can be programmed at 5V, only.
The TPI physical layer handles the basic low-level serial communication. The TPI physical layer
uses a bi-directional, half-duplex serial receiver and transmitter. The physical layer includes
serial-to-parallel and parallel-to-serial data conversion, start-of-frame detection, frame error
detection, parity error detection, parity generation and collision detection.
Physical Layer:
Access Layer:
– Synchronous Data Transfer
– Bi-directional, Half-duplex Receiver And Transmitter
– Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits
– Parity Error Detection, Frame Error Detection And Break Character Detection
– Parity Generation And Collision Detection
– Automatic Guard Time Insertion Between Data Reception And Transmission
– Communication Based On Messages
– Automatic Exception Handling Mechanism
– Compact Instruction Set
– NVM Programming Access Control
– Tiny Programming Interface Control And Status Space Access Control
– Data Space Access Control
14-1.
TPIDATA
TPICLK
RESET
TINY PROGRAMMING INTERFACE (TPI)
PHYSICAL
LAYER
“Memory Programming” on page
ACCESS
LAYER
108.
DATA BUS
ATtiny4/5/9/10
NON-VOLATILE
CONTROLLER
MEMORIES
NVM
97