DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 88

• Manufacturer Part Number: DF61543J40FPV
• Description: IC H8SX/1543 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1500r

Specifications of DF61543J40FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SCI, SSU
• Peripherals: DMA, Motor Control PWM, PWM, WDT
• Number Of I /o: 95
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561582S000BE - KIT DEV RSK H8SX/1582F
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Oscillator Type: -

Section 2 CPU
Legend:
d:
S:
D:
SD:
S/D:
S:4:
Notes: 1. Only @aa:16 is available.
Rev. 3.00 Sep. 24, 2009 Page 40 of 916
REJ09B0381-0300
Classifi-
cation
Bit
manipu-
lation
Branch
System
control
d:16 or d:32
Can be specified as a source operand.
Can be specified as a destination operand.
Can be specified as either a source or destination operand or both.
Can be specified as either a source or destination operand.
4-bit immediate data can be specified as a source operand.
2. @ERn+ as a source operand and @−ERn as a destination operand
3. Specified by ER5 as a source address and ER6 as a destination address for data
4. Size of data to be added with a displacement
5. Only @ERn− is available
6. When the number of bits to be shifted is 1, 2, 4, 8, or 16
7. When the number of bits to be shifted is specified by 5-bit immediate data or a general
8. Size of data to specify a branch condition
9. Byte when immediate or register direct, otherwise, word
10. Only @ERn+ is available
11. Only @−ERn is available
12. Not available in this LSI.
Instruction
BFLD
BFST
BRA/BS,
BRA/BC*
BSR/BS,
BSR/BC*
LDC (CCR, EXR)
LDC (VBR, SBR)
STC (CCR, EXR)
STC (VBR, SBR)
ANDC, ORC,
XORC
SLEEP
NOP
transfer.
register
8
8
Size
B
B
B
B
B/W*
L
B/W*
L
B
⎯
⎯
9
9
#xx
S
S
Rn
D
S
S
S
D
D
@ERn
S
D
S
S
S
D
@(d,ERn)
S
D
Addressing Mode
@(d,
RnL.B/
Rn.W/
ERn.L)
@−ERn/
@ERn+/
@ERn−/
@+ERn
S*
D*
10
11
@aa:8
S
D
S
S
@aa:16/
@aa:32
S
D
S
S
S
D
⎯
O
O